Commit 7e5f3146 authored by Kwon Tae-young's avatar Kwon Tae-young Committed by Shawn Guo
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arm64: dts: imx8mq-evk: add CD pinctrl for usdhc2 



Add CD pinctrl for usdhc2.

Signed-off-by: default avatarKwon Tae-young <tykwon@m2i.co.kr>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d05cd0dc

arch/arm64/boot/dts/freescale/imx8mq-evk.dts

+9 −3
Original line number Diff line number Diff line
@@ -403,9 +403,9 @@ 
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;

	assigned-clock-rates = <200000000>;

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc2>;

	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;

	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;

	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;

	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;

	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;

	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;

	vmmc-supply = <&reg_usdhc2_vmmc>;

	status = "okay";
@@ -565,6 +565,12 @@ 
		>;

	};



	pinctrl_usdhc2_gpio: usdhc2gpiogrp {

		fsl,pins = <

			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41

		>;

	};



	pinctrl_usdhc2: usdhc2grp {

		fsl,pins = <

			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83