Commit 7e4727f7 authored by Nancy.Lin's avatar Nancy.Lin Committed by Chun-Kuang Hu
Browse files

drm/mediatek: Add display merge advance config API for MT8195 



Add merge new advance config API. The original merge API is
mtk_ddp_comp_funcs function prototype. The API interface parameters
cannot be modified, so add a new config API for extension. This is
the preparation for ovl_adaptor merge control.

Signed-off-by: default avatarNancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: default avatarBo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20220620091930.27797-5-nancy.lin@mediatek.com/


Signed-off-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
parent f8946e2b

drivers/gpu/drm/mediatek/mtk_disp_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -63,6 +63,9 @@ void mtk_merge_config(struct device *dev, unsigned int width, 
		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);

void mtk_merge_start(struct device *dev);

void mtk_merge_stop(struct device *dev);

void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,

			      unsigned int h, unsigned int vrefresh, unsigned int bpc,

			      struct cmdq_pkt *cmdq_pkt);



void mtk_ovl_bgclr_in_on(struct device *dev);

void mtk_ovl_bgclr_in_off(struct device *dev);

drivers/gpu/drm/mediatek/mtk_disp_merge.c

+45 −7
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#define DISP_REG_MERGE_CTRL		0x000

#define MERGE_EN				1

#define DISP_REG_MERGE_CFG_0		0x010

#define DISP_REG_MERGE_CFG_1		0x014

#define DISP_REG_MERGE_CFG_4		0x020

#define DISP_REG_MERGE_CFG_10		0x038

/* no swap */
@@ -25,9 +26,12 @@ 
#define DISP_REG_MERGE_CFG_12		0x040

#define CFG_10_10_1PI_2PO_BUF_MODE		6

#define CFG_10_10_2PI_2PO_BUF_MODE		8

#define CFG_11_10_1PI_2PO_MERGE			18

#define FLD_CFG_MERGE_MODE			GENMASK(4, 0)

#define DISP_REG_MERGE_CFG_24		0x070

#define DISP_REG_MERGE_CFG_25		0x074

#define DISP_REG_MERGE_CFG_26		0x078

#define DISP_REG_MERGE_CFG_27		0x07c

#define DISP_REG_MERGE_CFG_36		0x0a0

#define ULTRA_EN				BIT(0)

#define PREULTRA_EN				BIT(4)
@@ -98,12 +102,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv, 
void mtk_merge_config(struct device *dev, unsigned int w,

		      unsigned int h, unsigned int vrefresh,

		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);

}



void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,

			      unsigned int h, unsigned int vrefresh, unsigned int bpc,

			      struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_disp_merge *priv = dev_get_drvdata(dev);

	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;



	if (!h || !w) {

		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);

	if (!h || !l_w) {

		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);

		return;

	}
@@ -112,14 +123,41 @@ void mtk_merge_config(struct device *dev, unsigned int w, 
		mode = CFG_10_10_2PI_2PO_BUF_MODE;

	}



	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,

	if (r_w)

		mode = CFG_11_10_1PI_2PO_MERGE;



	mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

		      DISP_REG_MERGE_CFG_0);

	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,

	mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,

		      DISP_REG_MERGE_CFG_1);

	mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,

		      DISP_REG_MERGE_CFG_4);

	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,

	/*

	 * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h

	 * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.

	 * If r_w > 0, the merge is in merge mode (input0 and input1 merge together),

	 * the input0 goes to SRAM0, and input1 goes to SRAM1.

	 * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and

	 * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.

	 */

	mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

		      DISP_REG_MERGE_CFG_24);

	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,

	if (r_w)

		mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,

			      DISP_REG_MERGE_CFG_25);

	else

		mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

			      DISP_REG_MERGE_CFG_25);



	/*

	 * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.

	 * Only take effect when the merge is setting to merge mode.

	 */

	mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,

		      DISP_REG_MERGE_CFG_26);

	mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,

		      DISP_REG_MERGE_CFG_27);



	mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,

			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);

	mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,