Commit 7e194533 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/gf100-/gf: split tpc state into its subunits 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 97af71fa

drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c

+11 −13
Original line number Diff line number Diff line
@@ -458,10 +458,7 @@ nv108_grctx_pack_gpc[] = { 
};



static const struct nvc0_graph_init

nv108_grctx_init_tpc_0[] = {

	{ 0x419848,   1, 0x04, 0x00000000 },

	{ 0x419864,   1, 0x04, 0x00000129 },

	{ 0x419888,   1, 0x04, 0x00000000 },

nv108_grctx_init_tex_0[] = {

	{ 0x419a00,   1, 0x04, 0x000100f0 },

	{ 0x419a04,   1, 0x04, 0x00000001 },

	{ 0x419a08,   1, 0x04, 0x00000421 },
@@ -472,14 +469,11 @@ nv108_grctx_init_tpc_0[] = { 
	{ 0x419a20,   1, 0x04, 0x00000800 },

	{ 0x419a30,   1, 0x04, 0x00000001 },

	{ 0x419ac4,   1, 0x04, 0x0037f440 },

	{ 0x419c00,   1, 0x04, 0x0000001a },

	{ 0x419c04,   1, 0x04, 0x80000006 },

	{ 0x419c08,   1, 0x04, 0x00000002 },

	{ 0x419c20,   1, 0x04, 0x00000000 },

	{ 0x419c24,   1, 0x04, 0x00084210 },

	{ 0x419c28,   1, 0x04, 0x3efbefbe },

	{ 0x419ce8,   1, 0x04, 0x00000000 },

	{ 0x419cf4,   1, 0x04, 0x00000203 },

	{}

};



static const struct nvc0_graph_init

nv108_grctx_init_sm_0[] = {

	{ 0x419e04,   1, 0x04, 0x00000000 },

	{ 0x419e08,   1, 0x04, 0x0000001d },

	{ 0x419e0c,   1, 0x04, 0x00000000 },
@@ -508,7 +502,11 @@ nv108_grctx_init_tpc_0[] = { 


static const struct nvc0_graph_pack

nv108_grctx_pack_tpc[] = {

	{ nv108_grctx_init_tpc_0 },

	{ nvd7_grctx_init_pe_0 },

	{ nv108_grctx_init_tex_0 },

	{ nvf0_grctx_init_mpc_0 },

	{ nvf0_grctx_init_l1c_0 },

	{ nv108_grctx_init_sm_0 },

	{}

};

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c

+39 −3
Original line number Diff line number Diff line
@@ -894,19 +894,29 @@ nvc0_grctx_pack_zcull[] = { 
	{}

};



static const struct nvc0_graph_init

nvc0_grctx_init_tpc_0[] = {

const struct nvc0_graph_init

nvc0_grctx_init_pe_0[] = {

	{ 0x419818,   1, 0x04, 0x00000000 },

	{ 0x41983c,   1, 0x04, 0x00038bc7 },

	{ 0x419848,   1, 0x04, 0x00000000 },

	{ 0x419864,   1, 0x04, 0x0000012a },

	{ 0x419888,   1, 0x04, 0x00000000 },

	{}

};



static const struct nvc0_graph_init

nvc0_grctx_init_tex_0[] = {

	{ 0x419a00,   1, 0x04, 0x000001f0 },

	{ 0x419a04,   1, 0x04, 0x00000001 },

	{ 0x419a08,   1, 0x04, 0x00000023 },

	{ 0x419a0c,   1, 0x04, 0x00020000 },

	{ 0x419a10,   1, 0x04, 0x00000000 },

	{ 0x419a14,   1, 0x04, 0x00000200 },

	{}

};



const struct nvc0_graph_init

nvc0_grctx_init_wwdx_0[] = {

	{ 0x419b00,   1, 0x04, 0x0a418820 },

	{ 0x419b04,   1, 0x04, 0x062080e6 },

	{ 0x419b08,   1, 0x04, 0x020398a4 },
@@ -916,15 +926,35 @@ nvc0_grctx_init_tpc_0[] = { 
	{ 0x419bd0,   1, 0x04, 0x00900103 },

	{ 0x419be0,   1, 0x04, 0x00000001 },

	{ 0x419be4,   1, 0x04, 0x00000000 },

	{}

};



const struct nvc0_graph_init

nvc0_grctx_init_mpc_0[] = {

	{ 0x419c00,   1, 0x04, 0x00000002 },

	{ 0x419c04,   1, 0x04, 0x00000006 },

	{ 0x419c08,   1, 0x04, 0x00000002 },

	{ 0x419c20,   1, 0x04, 0x00000000 },

	{}

};



static const struct nvc0_graph_init

nvc0_grctx_init_l1c_0[] = {

	{ 0x419cb0,   1, 0x04, 0x00060048 },

	{ 0x419ce8,   1, 0x04, 0x00000000 },

	{ 0x419cf4,   1, 0x04, 0x00000183 },

	{}

};



const struct nvc0_graph_init

nvc0_grctx_init_tpccs_0[] = {

	{ 0x419d20,   1, 0x04, 0x02180000 },

	{ 0x419d24,   1, 0x04, 0x00001fff },

	{}

};



static const struct nvc0_graph_init

nvc0_grctx_init_sm_0[] = {

	{ 0x419e04,   3, 0x04, 0x00000000 },

	{ 0x419e10,   1, 0x04, 0x00000002 },

	{ 0x419e44,   1, 0x04, 0x001beff2 },
@@ -938,7 +968,13 @@ nvc0_grctx_init_tpc_0[] = { 


const struct nvc0_graph_pack

nvc0_grctx_pack_tpc[] = {

	{ nvc0_grctx_init_tpc_0 },

	{ nvc0_grctx_init_pe_0 },

	{ nvc0_grctx_init_tex_0 },

	{ nvc0_grctx_init_wwdx_0 },

	{ nvc0_grctx_init_mpc_0 },

	{ nvc0_grctx_init_l1c_0 },

	{ nvc0_grctx_init_tpccs_0 },

	{ nvc0_grctx_init_sm_0 },

	{}

};

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h

+19 −0
Original line number Diff line number Diff line
@@ -105,11 +105,23 @@ extern const struct nvc0_graph_init nvc0_grctx_init_gcc_0[]; 
extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[];



extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[];

extern const struct nvc0_graph_init nvc0_grctx_init_pe_0[];

extern const struct nvc0_graph_init nvc0_grctx_init_wwdx_0[];

extern const struct nvc0_graph_init nvc0_grctx_init_mpc_0[];

extern const struct nvc0_graph_init nvc0_grctx_init_tpccs_0[];



extern const struct nvc0_graph_init nvc4_grctx_init_tex_0[];

extern const struct nvc0_graph_init nvc4_grctx_init_l1c_0[];

extern const struct nvc0_graph_init nvc4_grctx_init_sm_0[];



extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[];



extern const struct nvc0_graph_init nvc1_grctx_init_gpm_0[];



extern const struct nvc0_graph_init nvc1_grctx_init_pe_0[];

extern const struct nvc0_graph_init nvc1_grctx_init_wwdx_0[];

extern const struct nvc0_graph_init nvc1_grctx_init_tpccs_0[];



extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[];

extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[];
@@ -124,6 +136,10 @@ extern const struct nvc0_graph_init nvd9_grctx_init_prop_0[]; 
extern const struct nvc0_graph_init nvd9_grctx_init_gpc_unk_1[];

extern const struct nvc0_graph_init nvd9_grctx_init_crstr_0[];



extern const struct nvc0_graph_init nvd9_grctx_init_sm_0[];



extern const struct nvc0_graph_init nvd7_grctx_init_pe_0[];



extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[];

extern const struct nvc0_graph_init nve4_grctx_init_ds_0[];

extern const struct nvc0_graph_init nve4_grctx_init_scc_0[];
@@ -137,5 +153,8 @@ extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[]; 


extern const struct nvc0_graph_init nvf0_grctx_init_gpc_unk_2[];



extern const struct nvc0_graph_init nvf0_grctx_init_mpc_0[];

extern const struct nvc0_graph_init nvf0_grctx_init_l1c_0[];





#endif

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c

+19 −28
Original line number Diff line number Diff line
@@ -678,22 +678,18 @@ nvc1_grctx_pack_gpc[] = { 
	{}

};



static const struct nvc0_graph_init

nvc1_grctx_init_tpc_0[] = {

const struct nvc0_graph_init

nvc1_grctx_init_pe_0[] = {

	{ 0x419818,   1, 0x04, 0x00000000 },

	{ 0x41983c,   1, 0x04, 0x00038bc7 },

	{ 0x419848,   1, 0x04, 0x00000000 },

	{ 0x419864,   1, 0x04, 0x00000129 },

	{ 0x419888,   1, 0x04, 0x00000000 },

	{ 0x419a00,   1, 0x04, 0x000001f0 },

	{ 0x419a04,   1, 0x04, 0x00000001 },

	{ 0x419a08,   1, 0x04, 0x00000023 },

	{ 0x419a0c,   1, 0x04, 0x00020000 },

	{ 0x419a10,   1, 0x04, 0x00000000 },

	{ 0x419a14,   1, 0x04, 0x00000200 },

	{ 0x419a1c,   1, 0x04, 0x00000000 },

	{ 0x419a20,   1, 0x04, 0x00000800 },

	{ 0x419ac4,   1, 0x04, 0x0007f440 },

	{}

};



const struct nvc0_graph_init

nvc1_grctx_init_wwdx_0[] = {

	{ 0x419b00,   1, 0x04, 0x0a418820 },

	{ 0x419b04,   1, 0x04, 0x062080e6 },

	{ 0x419b08,   1, 0x04, 0x020398a4 },
@@ -703,31 +699,26 @@ nvc1_grctx_init_tpc_0[] = { 
	{ 0x419bd0,   1, 0x04, 0x00900103 },

	{ 0x419be0,   1, 0x04, 0x00400001 },

	{ 0x419be4,   1, 0x04, 0x00000000 },

	{ 0x419c00,   1, 0x04, 0x00000002 },

	{ 0x419c04,   1, 0x04, 0x00000006 },

	{ 0x419c08,   1, 0x04, 0x00000002 },

	{ 0x419c20,   1, 0x04, 0x00000000 },

	{ 0x419cb0,   1, 0x04, 0x00020048 },

	{ 0x419ce8,   1, 0x04, 0x00000000 },

	{ 0x419cf4,   1, 0x04, 0x00000183 },

	{}

};



const struct nvc0_graph_init

nvc1_grctx_init_tpccs_0[] = {

	{ 0x419d20,   1, 0x04, 0x12180000 },

	{ 0x419d24,   1, 0x04, 0x00001fff },

	{ 0x419d44,   1, 0x04, 0x02180218 },

	{ 0x419e04,   3, 0x04, 0x00000000 },

	{ 0x419e10,   1, 0x04, 0x00000002 },

	{ 0x419e44,   1, 0x04, 0x001beff2 },

	{ 0x419e48,   1, 0x04, 0x00000000 },

	{ 0x419e4c,   1, 0x04, 0x0000000f },

	{ 0x419e50,  17, 0x04, 0x00000000 },

	{ 0x419e98,   1, 0x04, 0x00000000 },

	{ 0x419ee0,   1, 0x04, 0x00011110 },

	{ 0x419f30,  11, 0x04, 0x00000000 },

	{}

};



static const struct nvc0_graph_pack

nvc1_grctx_pack_tpc[] = {

	{ nvc1_grctx_init_tpc_0 },

	{ nvc1_grctx_init_pe_0 },

	{ nvc4_grctx_init_tex_0 },

	{ nvc1_grctx_init_wwdx_0 },

	{ nvc0_grctx_init_mpc_0 },

	{ nvc4_grctx_init_l1c_0 },

	{ nvc1_grctx_init_tpccs_0 },

	{ nvc4_grctx_init_sm_0 },

	{}

};

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c

+19 −23
Original line number Diff line number Diff line
@@ -28,13 +28,8 @@ 
 * PGRAPH context register lists

 ******************************************************************************/



static const struct nvc0_graph_init

nvc4_grctx_init_tpc_0[] = {

	{ 0x419818,   1, 0x04, 0x00000000 },

	{ 0x41983c,   1, 0x04, 0x00038bc7 },

	{ 0x419848,   1, 0x04, 0x00000000 },

	{ 0x419864,   1, 0x04, 0x0000012a },

	{ 0x419888,   1, 0x04, 0x00000000 },

const struct nvc0_graph_init

nvc4_grctx_init_tex_0[] = {

	{ 0x419a00,   1, 0x04, 0x000001f0 },

	{ 0x419a04,   1, 0x04, 0x00000001 },

	{ 0x419a08,   1, 0x04, 0x00000023 },
@@ -44,24 +39,19 @@ nvc4_grctx_init_tpc_0[] = { 
	{ 0x419a1c,   1, 0x04, 0x00000000 },

	{ 0x419a20,   1, 0x04, 0x00000800 },

	{ 0x419ac4,   1, 0x04, 0x0007f440 },

	{ 0x419b00,   1, 0x04, 0x0a418820 },

	{ 0x419b04,   1, 0x04, 0x062080e6 },

	{ 0x419b08,   1, 0x04, 0x020398a4 },

	{ 0x419b0c,   1, 0x04, 0x0e629062 },

	{ 0x419b10,   1, 0x04, 0x0a418820 },

	{ 0x419b14,   1, 0x04, 0x000000e6 },

	{ 0x419bd0,   1, 0x04, 0x00900103 },

	{ 0x419be0,   1, 0x04, 0x00000001 },

	{ 0x419be4,   1, 0x04, 0x00000000 },

	{ 0x419c00,   1, 0x04, 0x00000002 },

	{ 0x419c04,   1, 0x04, 0x00000006 },

	{ 0x419c08,   1, 0x04, 0x00000002 },

	{ 0x419c20,   1, 0x04, 0x00000000 },

	{}

};



const struct nvc0_graph_init

nvc4_grctx_init_l1c_0[] = {

	{ 0x419cb0,   1, 0x04, 0x00020048 },

	{ 0x419ce8,   1, 0x04, 0x00000000 },

	{ 0x419cf4,   1, 0x04, 0x00000183 },

	{ 0x419d20,   1, 0x04, 0x02180000 },

	{ 0x419d24,   1, 0x04, 0x00001fff },

	{}

};



const struct nvc0_graph_init

nvc4_grctx_init_sm_0[] = {

	{ 0x419e04,   3, 0x04, 0x00000000 },

	{ 0x419e10,   1, 0x04, 0x00000002 },

	{ 0x419e44,   1, 0x04, 0x001beff2 },
@@ -76,7 +66,13 @@ nvc4_grctx_init_tpc_0[] = { 


static const struct nvc0_graph_pack

nvc4_grctx_pack_tpc[] = {

	{ nvc4_grctx_init_tpc_0 },

	{ nvc0_grctx_init_pe_0 },

	{ nvc4_grctx_init_tex_0 },

	{ nvc0_grctx_init_wwdx_0 },

	{ nvc0_grctx_init_mpc_0 },

	{ nvc4_grctx_init_l1c_0 },

	{ nvc0_grctx_init_tpccs_0 },

	{ nvc4_grctx_init_sm_0 },

	{}

};