Commit 7df71709 authored by Joey Gouly's avatar Joey Gouly Committed by Catalin Marinas
Browse files

arm64: disable EL2 traps for PIE 



Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be
accessed from by EL1.

Signed-off-by: default avatarJoey Gouly <joey.gouly@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20230606145859.697944-15-joey.gouly@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent fa4cdcca

arch/arm64/include/asm/el2_setup.h

+10 −1
Original line number Diff line number Diff line
@@ -159,12 +159,21 @@ 
	mov	x0, xzr

	mrs	x1, id_aa64pfr1_el1

	ubfx	x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4

	cbz	x1, .Lset_fgt_\@

	cbz	x1, .Lset_pie_fgt_\@



	/* Disable nVHE traps of TPIDR2 and SMPRI */

	orr	x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK

	orr	x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK



.Lset_pie_fgt_\@:

	mrs_s	x1, SYS_ID_AA64MMFR3_EL1

	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4

	cbz	x1, .Lset_fgt_\@



	/* Disable trapping of PIR_EL1 / PIRE0_EL1 */

	orr	x0, x0, #HFGxTR_EL2_nPIR_EL1

	orr	x0, x0, #HFGxTR_EL2_nPIRE0_EL1



.Lset_fgt_\@:

	msr_s	SYS_HFGRTR_EL2, x0

	msr_s	SYS_HFGWTR_EL2, x0

arch/arm64/include/asm/kvm_arm.h

+2 −2
Original line number Diff line number Diff line
@@ -93,8 +93,8 @@ 
#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)

#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)



#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME)

#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn)

#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En)

#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)



/* TCR_EL2 Registers bits */

#define TCR_EL2_RES1		((1U << 31) | (1 << 23))