Unverified Commit 7de1e2ce authored Apr 29, 2024 by openeuler-ci-bot Committed by Gitee Apr 29, 2024

!6651 [OLK - 6.6]net: hns3: add support for Hisilicon ptp sync device

Merge Pull Request from: @chen-hao418 
 
    net: hns3: add support for Hisilicon ptp sync device

    driver inclusion
    category: feature
    bugzilla: https://gitee.com/openeuler/kernel/issues/I9I46F


    CVE: NA

    ----------------------------------------------------------------------

    The hns3 driver provide ptp driver to get 1588 clock from
    ethernet, but only the first PF on main chip can support this,
    so, if getting ptp time from other chip, may have some bus
    latency. The PTP sync device use to eliminate the bus latency.

    Signed-off-by: Yonglong Liu <liuyonglong@huawei.com>
 
 
Link:https://gitee.com/openeuler/kernel/pulls/6651

 

Reviewed-by: Liu Chao <liuchao173@huawei.com>
Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com>

parents 3c43d146 e6aa0ecf

MAINTAINERS

+5 −0

Original line number	Diff line number	Diff line
		@@ -9523,6 +9523,11 @@ S: Maintained
		W: http://www.hisilicon.com
		F: drivers/spi/spi-hisi-sfc-v3xx.c

		HISILICON HNS3 PTP SYNC DRIVER
		M: Yonglong Liu <liuyonglong@huawei.com>
		S: Supported
		F: drivers/ptp/ptp_hisi.c

		HISILICON ZIP Controller DRIVER
		M: Yang Shen <shenyang39@huawei.com>
		M: Zhou Wang <wangzhou1@hisilicon.com>

arch/arm64/configs/openeuler_defconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -3881,6 +3881,7 @@ CONFIG_PTP_1588_CLOCK_KVM=y
		# CONFIG_PTP_1588_CLOCK_MOCK is not set
		# CONFIG_PTP_1588_CLOCK_OCP is not set
		# end of PTP clock support
		CONFIG_PTP_HISI=m

		CONFIG_PINCTRL=y
		CONFIG_PINMUX=y

drivers/ptp/Kconfig

+12 −0

Original line number	Diff line number	Diff line
		@@ -211,4 +211,16 @@ config PTP_DFL_TOD
		To compile this driver as a module, choose M here: the module
		will be called ptp_dfl_tod.

		config PTP_HISI
		tristate "HiSilicon PTP sync platform driver"
		depends on ARM64
		help
		PTP sync driver work on multichip system, eliminates the bus latency
		between multichip, and provide a higher precision clock source. But
		the clock source of PTP sync device is from the RTC of HNS3 ethernet
		device, so, if you want the PTP sync device works, you must enable
		HNS3 driver also.

		If unsure, say N.

		endmenu

drivers/ptp/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -20,3 +20,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_MOCK) += ptp_mock.o
		obj-$(CONFIG_PTP_1588_CLOCK_VMW) += ptp_vmw.o
		obj-$(CONFIG_PTP_1588_CLOCK_OCP) += ptp_ocp.o
		obj-$(CONFIG_PTP_DFL_TOD) += ptp_dfl_tod.o
		obj-$(CONFIG_PTP_HISI) += ptp_hisi.o

drivers/ptp/ptp_hisi.c

0 → 100644

+1027 −0

File added.

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