Commit 7dd9b5a1 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Move __get_fault_info() and co into their own include file 



In order to avoid including the whole of the switching helpers
in unrelated files, move the __get_fault_info() and related helpers
into their own include file.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Link: https://lore.kernel.org/r/20211010145636.1950948-2-tabba@google.com
parent 9e1ff307

arch/arm64/kvm/hyp/include/hyp/fault.h

0 → 100644
+75 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (C) 2015 - ARM Ltd

 * Author: Marc Zyngier <marc.zyngier@arm.com>

 */



#ifndef __ARM64_KVM_HYP_FAULT_H__

#define __ARM64_KVM_HYP_FAULT_H__



#include <asm/kvm_asm.h>

#include <asm/kvm_emulate.h>

#include <asm/kvm_hyp.h>

#include <asm/kvm_mmu.h>



static inline bool __translate_far_to_hpfar(u64 far, u64 *hpfar)

{

	u64 par, tmp;



	/*

	 * Resolve the IPA the hard way using the guest VA.

	 *

	 * Stage-1 translation already validated the memory access

	 * rights. As such, we can use the EL1 translation regime, and

	 * don't have to distinguish between EL0 and EL1 access.

	 *

	 * We do need to save/restore PAR_EL1 though, as we haven't

	 * saved the guest context yet, and we may return early...

	 */

	par = read_sysreg_par();

	if (!__kvm_at("s1e1r", far))

		tmp = read_sysreg_par();

	else

		tmp = SYS_PAR_EL1_F; /* back to the guest */

	write_sysreg(par, par_el1);



	if (unlikely(tmp & SYS_PAR_EL1_F))

		return false; /* Translation failed, back to guest */



	/* Convert PAR to HPFAR format */

	*hpfar = PAR_TO_HPFAR(tmp);

	return true;

}



static inline bool __get_fault_info(u64 esr, struct kvm_vcpu_fault_info *fault)

{

	u64 hpfar, far;



	far = read_sysreg_el2(SYS_FAR);



	/*

	 * The HPFAR can be invalid if the stage 2 fault did not

	 * happen during a stage 1 page table walk (the ESR_EL2.S1PTW

	 * bit is clear) and one of the two following cases are true:

	 *   1. The fault was due to a permission fault

	 *   2. The processor carries errata 834220

	 *

	 * Therefore, for all non S1PTW faults where we either have a

	 * permission fault or the errata workaround is enabled, we

	 * resolve the IPA using the AT instruction.

	 */

	if (!(esr & ESR_ELx_S1PTW) &&

	    (cpus_have_final_cap(ARM64_WORKAROUND_834220) ||

	     (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {

		if (!__translate_far_to_hpfar(far, &hpfar))

			return false;

	} else {

		hpfar = read_sysreg(hpfar_el2);

	}



	fault->far_el2 = far;

	fault->hpfar_el2 = hpfar;

	return true;

}



#endif

arch/arm64/kvm/hyp/include/hyp/switch.h

+1 −60
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#define __ARM64_KVM_HYP_SWITCH_H__



#include <hyp/adjust_pc.h>

#include <hyp/fault.h>



#include <linux/arm-smccc.h>

#include <linux/kvm_host.h>
@@ -133,66 +134,6 @@ static inline void ___deactivate_traps(struct kvm_vcpu *vcpu) 
	}

}



static inline bool __translate_far_to_hpfar(u64 far, u64 *hpfar)

{

	u64 par, tmp;



	/*

	 * Resolve the IPA the hard way using the guest VA.

	 *

	 * Stage-1 translation already validated the memory access

	 * rights. As such, we can use the EL1 translation regime, and

	 * don't have to distinguish between EL0 and EL1 access.

	 *

	 * We do need to save/restore PAR_EL1 though, as we haven't

	 * saved the guest context yet, and we may return early...

	 */

	par = read_sysreg_par();

	if (!__kvm_at("s1e1r", far))

		tmp = read_sysreg_par();

	else

		tmp = SYS_PAR_EL1_F; /* back to the guest */

	write_sysreg(par, par_el1);



	if (unlikely(tmp & SYS_PAR_EL1_F))

		return false; /* Translation failed, back to guest */



	/* Convert PAR to HPFAR format */

	*hpfar = PAR_TO_HPFAR(tmp);

	return true;

}



static inline bool __get_fault_info(u64 esr, struct kvm_vcpu_fault_info *fault)

{

	u64 hpfar, far;



	far = read_sysreg_el2(SYS_FAR);



	/*

	 * The HPFAR can be invalid if the stage 2 fault did not

	 * happen during a stage 1 page table walk (the ESR_EL2.S1PTW

	 * bit is clear) and one of the two following cases are true:

	 *   1. The fault was due to a permission fault

	 *   2. The processor carries errata 834220

	 *

	 * Therefore, for all non S1PTW faults where we either have a

	 * permission fault or the errata workaround is enabled, we

	 * resolve the IPA using the AT instruction.

	 */

	if (!(esr & ESR_ELx_S1PTW) &&

	    (cpus_have_final_cap(ARM64_WORKAROUND_834220) ||

	     (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {

		if (!__translate_far_to_hpfar(far, &hpfar))

			return false;

	} else {

		hpfar = read_sysreg(hpfar_el2);

	}



	fault->far_el2 = far;

	fault->hpfar_el2 = hpfar;

	return true;

}



static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)

{

	u8 ec;

arch/arm64/kvm/hyp/nvhe/mem_protect.c

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
#include <asm/kvm_pgtable.h>

#include <asm/stage2_pgtable.h>



#include <hyp/switch.h>

#include <hyp/fault.h>



#include <nvhe/gfp.h>

#include <nvhe/memory.h>