Commit 7dbe5a7a authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Stephen Boyd
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dt-bindings: clock: Add support for LPASS Always ON Controller



Always ON Clock controller is a block inside LPASS which controls
1 Glitch free muxes to LPASS codec Macros.

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20201026120221.18984-3-srinivas.kandagatla@linaro.org


Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent a6dee2fe
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for LPASS Always ON Clock Controller on SM8250 SoCs

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell.
  See include/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h for the full list
  of Audio Clock controller clock IDs.

properties:
  compatible:
    const: qcom,sm8250-lpass-aon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: LPASS Core voting clock
      - description: Glitch Free Mux register clock

  clock-names:
    items:
      - const: core
      - const: bus

required:
  - compatible
  - reg
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
    #include <dt-bindings/sound/qcom,q6afe.h>
    clock-controller@3800000 {
      #clock-cells = <1>;
      compatible = "qcom,sm8250-lpass-aon";
      reg = <0x03380000 0x40000>;
      clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
               <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
      clock-names = "core", "bus";
    };
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/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _DT_BINDINGS_CLK_LPASS_AONCC_SM8250_H
#define _DT_BINDINGS_CLK_LPASS_AONCC_SM8250_H

/* from AOCC */
#define LPASS_CDC_VA_MCLK				0
#define LPASS_CDC_TX_NPL				1
#define LPASS_CDC_TX_MCLK				2

#endif /* _DT_BINDINGS_CLK_LPASS_AONCC_SM8250_H */