Commit 7dbd121a authored by Taniya Das's avatar Taniya Das Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sc7280: Add cpufreq hw node 



Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SC7280 SoCs.

Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1618020280-5470-2-git-send-email-tdas@codeaurora.org


[bjorn: Dropped reg-names]
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 822c8f2a

arch/arm64/boot/dts/qcom/sc7280.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ 
					   &LITTLE_CPU_SLEEP_1

					   &CLUSTER_SLEEP_0>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

				compatible = "cache";
@@ -90,6 +91,7 @@ 
					   &LITTLE_CPU_SLEEP_1

					   &CLUSTER_SLEEP_0>;

			next-level-cache = <&L2_100>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			#cooling-cells = <2>;

			L2_100: l2-cache {

				compatible = "cache";
@@ -106,6 +108,7 @@ 
					   &LITTLE_CPU_SLEEP_1

					   &CLUSTER_SLEEP_0>;

			next-level-cache = <&L2_200>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			#cooling-cells = <2>;

			L2_200: l2-cache {

				compatible = "cache";
@@ -122,6 +125,7 @@ 
					   &LITTLE_CPU_SLEEP_1

					   &CLUSTER_SLEEP_0>;

			next-level-cache = <&L2_300>;

			qcom,freq-domain = <&cpufreq_hw 0>;

			#cooling-cells = <2>;

			L2_300: l2-cache {

				compatible = "cache";
@@ -138,6 +142,7 @@ 
					   &BIG_CPU_SLEEP_1

					   &CLUSTER_SLEEP_0>;

			next-level-cache = <&L2_400>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			#cooling-cells = <2>;

			L2_400: l2-cache {

				compatible = "cache";
@@ -154,6 +159,7 @@ 
					   &BIG_CPU_SLEEP_1

					   &CLUSTER_SLEEP_0>;

			next-level-cache = <&L2_500>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			#cooling-cells = <2>;

			L2_500: l2-cache {

				compatible = "cache";
@@ -170,6 +176,7 @@ 
					   &BIG_CPU_SLEEP_1

					   &CLUSTER_SLEEP_0>;

			next-level-cache = <&L2_600>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			#cooling-cells = <2>;

			L2_600: l2-cache {

				compatible = "cache";
@@ -186,6 +193,7 @@ 
					   &BIG_CPU_SLEEP_1

					   &CLUSTER_SLEEP_0>;

			next-level-cache = <&L2_700>;

			qcom,freq-domain = <&cpufreq_hw 1>;

			#cooling-cells = <2>;

			L2_700: l2-cache {

				compatible = "cache";
@@ -1147,6 +1155,16 @@ 
				#clock-cells = <1>;

			};

		};



		cpufreq_hw: cpufreq@18591000 {

			compatible = "qcom,cpufreq-epss";

			reg = <0 0x18591000 0 0x1000>,

			      <0 0x18592000 0 0x1000>,

			      <0 0x18593000 0 0x1000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;

			clock-names = "xo", "alternate";

			#freq-domain-cells = <1>;

		};

	};



	thermal_zones: thermal-zones {