Commit 7d9869ac authored by James Clark's avatar James Clark Committed by Junhao He
Browse files

arm64: perf: Include threshold control fields in PMEVTYPER mask

mainline inclusion
from mainline-v6.8-rc1
commit 3115ee021bfb04efde2e96507bfcc1330261a6a1
category: cleanup
bugzilla: https://gitee.com/openeuler/kernel/issues/I9Q7QP
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=3115ee021bfb04efde2e96507bfcc1330261a6a1



--------------------------------

FEAT_PMUv3_TH (Armv8.8) adds two new fields to PMEVTYPER, so include
them in the mask. These aren't writable on 32 bit kernels as they are in
the high part of the register, so only include them for arm64.

It would be difficult to do this statically in the asm header files for
each platform without resulting in circular includes or #ifdefs inline
in the code. For that reason the ARMV8_PMU_EVTYPE_MASK definition has
been removed and the mask is constructed programmatically.

Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: default avatarJames Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20231211161331.1277825-6-james.clark@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarJunhao He <hejunhao3@huawei.com>
parent e42a6968
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+8 −1
Original line number Diff line number Diff line
@@ -558,8 +558,15 @@ static void armv8pmu_write_counter(struct perf_event *event, u64 value)
static void armv8pmu_write_evtype(int idx, u32 val)
{
	u32 counter = ARMV8_IDX_TO_COUNTER(idx);
	unsigned long mask = ARMV8_PMU_EVTYPE_EVENT |
			     ARMV8_PMU_INCLUDE_EL2 |
			     ARMV8_PMU_EXCLUDE_EL0 |
			     ARMV8_PMU_EXCLUDE_EL1;

	val &= ARMV8_PMU_EVTYPE_MASK;
	if (IS_ENABLED(CONFIG_ARM64))
		mask |= ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH;

	val &= mask;
	write_pmevtypern(counter, val);
}

+2 −1
Original line number Diff line number Diff line
@@ -233,8 +233,9 @@
/*
 * PMXEVTYPER: Event selection reg
 */
#define ARMV8_PMU_EVTYPE_MASK	0xc800ffff	/* Mask for writable bits */
#define ARMV8_PMU_EVTYPE_EVENT	GENMASK(15, 0)	/* Mask for EVENT bits */
#define ARMV8_PMU_EVTYPE_TH	GENMASK(43, 32)
#define ARMV8_PMU_EVTYPE_TC	GENMASK(63, 61)

/*
 * Event filters for PMUv3