Commit 7d805acc authored Sep 03, 2019 by Nicholas Piggin Committed by Michael Ellerman Sep 05, 2019

powerpc/64s: remove unnecessary translation cache flushes at boot



The various translation structure invalidations performed in early boot
when the MMU is off are not required, because everything is invalidated
immediately before a CPU first enables its MMU (see early_init_mmu
and early_init_mmu_secondary).

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190902152931.17840-6-npiggin@gmail.com

parent 7e71c428

arch/powerpc/mm/book3s64/hash_utils.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -825,7 +825,7 @@ static void __init hash_init_partition_table(phys_addr_t hash_table,
	* For now, UPRT is 0 and we have no segment table.		* For now, UPRT is 0 and we have no segment table.
	*/		*/
	htab_size = __ilog2(htab_size) - 18;		htab_size = __ilog2(htab_size) - 18;
	mmu_partition_table_set_entry(0, hash_table \| htab_size, 0, true);		mmu_partition_table_set_entry(0, hash_table \| htab_size, 0, false);
	pr_info("Partition table %p\n", partition_tb);		pr_info("Partition table %p\n", partition_tb);
	}		}

arch/powerpc/mm/book3s64/pgtable.c

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -252,6 +252,11 @@ void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
	pr_info("PATE registered by ultravisor: dw0 = 0x%lx, dw1 = 0x%lx\n",		pr_info("PATE registered by ultravisor: dw0 = 0x%lx, dw1 = 0x%lx\n",
	dw0, dw1);		dw0, dw1);
	} else if (flush) {		} else if (flush) {
			/*
			* Boot does not need to flush, because MMU is off and each
			* CPU does a tlbiel_all() before switching them on, which
			* flushes everything.
			*/
	flush_partition(lpid, (old & PATB_HR));		flush_partition(lpid, (old & PATB_HR));
	}		}
	}		}

arch/powerpc/mm/book3s64/radix_pgtable.c

+1 −7

Original line number	Original line	Diff line number	Diff line
	@@ -396,13 +396,7 @@ static void __init radix_init_partition_table(void)
	rts_field = radix__get_tree_size();		rts_field = radix__get_tree_size();
	dw0 = rts_field \| __pa(init_mm.pgd) \| RADIX_PGD_INDEX_SIZE \| PATB_HR;		dw0 = rts_field \| __pa(init_mm.pgd) \| RADIX_PGD_INDEX_SIZE \| PATB_HR;
	dw1 = __pa(process_tb) \| (PRTB_SIZE_SHIFT - 12) \| PATB_GR;		dw1 = __pa(process_tb) \| (PRTB_SIZE_SHIFT - 12) \| PATB_GR;
	mmu_partition_table_set_entry(0, dw0, dw1, true);		mmu_partition_table_set_entry(0, dw0, dw1, false);

	asm volatile("ptesync" : : : "memory");
	asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
	"r" (TLBIEL_INVAL_SET_LPID), "r" (0));
	asm volatile("eieio; tlbsync; ptesync" : : : "memory");
	trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);

	pr_info("Initializing Radix MMU\n");		pr_info("Initializing Radix MMU\n");
	pr_info("Partition table %p\n", partition_tb);		pr_info("Partition table %p\n", partition_tb);

arch/powerpc/platforms/pseries/lpar.c

+0 −5

Original line number	Original line	Diff line number	Diff line
	@@ -1549,11 +1549,6 @@ void radix_init_pseries(void)

	pseries_lpar_register_process_table(__pa(process_tb),		pseries_lpar_register_process_table(__pa(process_tb),
	0, PRTB_SIZE_SHIFT - 12);		0, PRTB_SIZE_SHIFT - 12);
	asm volatile("ptesync" : : : "memory");
	asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
	"r" (TLBIEL_INVAL_SET_LPID), "r" (0));
	asm volatile("eieio; tlbsync; ptesync" : : : "memory");
	trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
	}		}

	#ifdef CONFIG_PPC_SMLPAR		#ifdef CONFIG_PPC_SMLPAR