Commit 7d4705b3 authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu/mes11: add mes11 misc op 



Add misc op commands in mes11.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cff35798

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+53 −0
Original line number Diff line number Diff line
@@ -274,6 +274,58 @@ static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 
			&mes_status_pkt, sizeof(mes_status_pkt));

}



static int mes_v11_0_misc_op(struct amdgpu_mes *mes,

			     struct mes_misc_op_input *input)

{

	union MESAPI__MISC misc_pkt;



	memset(&misc_pkt, 0, sizeof(misc_pkt));



	misc_pkt.header.type = MES_API_TYPE_SCHEDULER;

	misc_pkt.header.opcode = MES_SCH_API_MISC;

	misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;



	switch (input->op) {

	case MES_MISC_OP_READ_REG:

		misc_pkt.opcode = MESAPI_MISC__READ_REG;

		misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;

		misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;

		break;

	case MES_MISC_OP_WRITE_REG:

		misc_pkt.opcode = MESAPI_MISC__WRITE_REG;

		misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;

		misc_pkt.write_reg.reg_value = input->write_reg.reg_value;

		break;

	case MES_MISC_OP_WRM_REG_WAIT:

		misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;

		misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;

		misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;

		misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;

		misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;

		misc_pkt.wait_reg_mem.reg_offset2 = 0;

		break;

	case MES_MISC_OP_WRM_REG_WR_WAIT:

		misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;

		misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;

		misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;

		misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;

		misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;

		misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;

		break;

	default:

		DRM_ERROR("unsupported misc op (%d) \n", input->op);

		return -EINVAL;

	}



	misc_pkt.api_status.api_completion_fence_addr =

		mes->ring.fence_drv.gpu_addr;

	misc_pkt.api_status.api_completion_fence_value =

		++mes->ring.fence_drv.sync_seq;



	return mes_v11_0_submit_pkt_and_poll_completion(mes,

			&misc_pkt, sizeof(misc_pkt));

}



static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)

{

	int i;
@@ -336,6 +388,7 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 
	.unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,

	.suspend_gang = mes_v11_0_suspend_gang,

	.resume_gang = mes_v11_0_resume_gang,

	.misc_op = mes_v11_0_misc_op,

};



static int mes_v11_0_init_microcode(struct amdgpu_device *adev,