Commit 7d456172 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Tweak plane ddb allocation tracking 



Let's store the plane allocation in a manner which more closely
matches how the hw operates. That is, we store the packed/CbCr
ddb in one struct, and the Y ddb in another. Currently we're
storing packed/Y in one struct, CbCr in the other.

This also works pretty well for icl+ where the UV plane is
the main plane and the Y plane is subservient to it. Although
in this case we do not even use ddb_y as we do the ddb allocation
in terms of hw planes.

v2: Rebase

Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220303191207.27931-2-ville.syrjala@linux.intel.com
parent f99f5569

drivers/gpu/drm/i915/display/intel_atomic_plane.c

+14 −18
Original line number Diff line number Diff line
@@ -616,8 +616,8 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, 
static struct intel_plane *

skl_next_plane_to_commit(struct intel_atomic_state *state,

			 struct intel_crtc *crtc,

			 struct skl_ddb_entry entries_y[I915_MAX_PLANES],

			 struct skl_ddb_entry entries_uv[I915_MAX_PLANES],

			 struct skl_ddb_entry ddb[I915_MAX_PLANES],

			 struct skl_ddb_entry ddb_y[I915_MAX_PLANES],

			 unsigned int *update_mask)

{

	struct intel_crtc_state *crtc_state =
@@ -636,17 +636,15 @@ skl_next_plane_to_commit(struct intel_atomic_state *state, 
		    !(*update_mask & BIT(plane_id)))

			continue;



		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],

						entries_y,

						I915_MAX_PLANES, plane_id) ||

		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],

						entries_uv,

						I915_MAX_PLANES, plane_id))

		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],

						ddb, I915_MAX_PLANES, plane_id) ||

		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],

						ddb_y, I915_MAX_PLANES, plane_id))

			continue;



		*update_mask &= ~BIT(plane_id);

		entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];

		entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];

		ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];

		ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];



		return plane;

	}
@@ -728,19 +726,17 @@ static void skl_crtc_planes_update_arm(struct intel_atomic_state *state, 
		intel_atomic_get_old_crtc_state(state, crtc);

	struct intel_crtc_state *new_crtc_state =

		intel_atomic_get_new_crtc_state(state, crtc);

	struct skl_ddb_entry entries_y[I915_MAX_PLANES];

	struct skl_ddb_entry entries_uv[I915_MAX_PLANES];

	struct skl_ddb_entry ddb[I915_MAX_PLANES];

	struct skl_ddb_entry ddb_y[I915_MAX_PLANES];

	u32 update_mask = new_crtc_state->update_planes;

	struct intel_plane *plane;



	memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,

	memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,

	       sizeof(old_crtc_state->wm.skl.plane_ddb));

	memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,

	       sizeof(old_crtc_state->wm.skl.plane_ddb_y));

	memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,

	       sizeof(old_crtc_state->wm.skl.plane_ddb_uv));



	while ((plane = skl_next_plane_to_commit(state, crtc,

						 entries_y, entries_uv,

						 &update_mask))) {

	while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {

		struct intel_plane_state *new_plane_state =

			intel_atomic_get_new_plane_state(state, plane);

drivers/gpu/drm/i915/display/intel_bw.c

+3 −3
Original line number Diff line number Diff line
@@ -688,16 +688,16 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, 
		return;



	for_each_plane_id_on_crtc(crtc, plane_id) {

		const struct skl_ddb_entry *ddb =

			&crtc_state->wm.skl.plane_ddb[plane_id];

		const struct skl_ddb_entry *ddb_y =

			&crtc_state->wm.skl.plane_ddb_y[plane_id];

		const struct skl_ddb_entry *ddb_uv =

			&crtc_state->wm.skl.plane_ddb_uv[plane_id];

		unsigned int data_rate = crtc_state->data_rate[plane_id];

		unsigned int dbuf_mask = 0;

		enum dbuf_slice slice;



		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb);

		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);

		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_uv);



		/*

		 * FIXME: To calculate that more properly we probably

drivers/gpu/drm/i915/display/intel_display.c

+4 −4
Original line number Diff line number Diff line
@@ -6508,8 +6508,8 @@ static void verify_wm_state(struct intel_crtc *crtc, 
{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct skl_hw_state {

		struct skl_ddb_entry ddb[I915_MAX_PLANES];

		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];

		struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];

		struct skl_pipe_wm wm;

	} *hw;

	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
@@ -6526,7 +6526,7 @@ static void verify_wm_state(struct intel_crtc *crtc, 


	skl_pipe_wm_get_hw_state(crtc, &hw->wm);



	skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);

	skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);



	hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
@@ -6608,8 +6608,8 @@ static void verify_wm_state(struct intel_crtc *crtc, 
		}



		/* DDB */

		hw_ddb_entry = &hw->ddb_y[plane->id];

		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];

		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];

		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];



		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {

			drm_err(&dev_priv->drm,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -1125,13 +1125,13 @@ static int i915_ddb_info(struct seq_file *m, void *unused) 
		seq_printf(m, "Pipe %c\n", pipe_name(pipe));



		for_each_plane_id_on_crtc(crtc, plane_id) {

			entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];

			entry = &crtc_state->wm.skl.plane_ddb[plane_id];

			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,

				   entry->start, entry->end,

				   skl_ddb_entry_size(entry));

		}



		entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];

		entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];

		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,

			   entry->end, skl_ddb_entry_size(entry));

	}

drivers/gpu/drm/i915/display/intel_display_types.h

+6 −1
Original line number Diff line number Diff line
@@ -846,8 +846,13 @@ struct intel_crtc_wm_state { 
			/* gen9+ only needs 1-step wm programming */

			struct skl_pipe_wm optimal;

			struct skl_ddb_entry ddb;

			/*

			 * pre-icl: for packed/planar CbCr

			 * icl+: for everything

			 */

			struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];

			/* pre-icl: for planar Y */

			struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];

			struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];

		} skl;



		struct {