Commit 7d296f36 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Parameterize R_PWR_CLK_STATE register definition 



At the moment we only use R_PWR_CLK_STATE in the context of the RCS
engine, but upcoming support for compute engines will start using
instances relative to the CCS engine base offsets.  Let's parameterize
the register and move it to the engine reg header.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220127234334.4016964-4-matthew.d.roper@intel.com
parent 66a19a3a

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

+2 −1
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 


#include "gem/i915_gem_pm.h"

#include "gt/intel_engine_pm.h"

#include "gt/intel_engine_regs.h"

#include "gt/intel_gt.h"

#include "gt/intel_gt_requests.h"

#include "gt/intel_reset.h"
@@ -894,7 +895,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v 
		return PTR_ERR(cmd);



	*cmd++ = MI_STORE_REGISTER_MEM_GEN8;

	*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);

	*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE));

	*cmd++ = lower_32_bits(vma->node.start);

	*cmd++ = upper_32_bits(vma->node.start);

	*cmd = MI_BATCH_BUFFER_END;

drivers/gpu/drm/i915/gt/intel_engine_regs.h

+15 −0
Original line number Diff line number Diff line
@@ -77,6 +77,21 @@ 
#define RING_INSTPM(base)			_MMIO((base) + 0xc0)

#define RING_CMD_CCTL(base)			_MMIO((base) + 0xc4)

#define ACTHD(base)				_MMIO((base) + 0xc8)

#define GEN8_R_PWR_CLK_STATE(base)		_MMIO((base) + 0xc8)

#define   GEN8_RPCS_ENABLE			(1 << 31)

#define   GEN8_RPCS_S_CNT_ENABLE		(1 << 18)

#define   GEN8_RPCS_S_CNT_SHIFT			15

#define   GEN8_RPCS_S_CNT_MASK			(0x7 << GEN8_RPCS_S_CNT_SHIFT)

#define   GEN11_RPCS_S_CNT_SHIFT		12

#define   GEN11_RPCS_S_CNT_MASK			(0x3f << GEN11_RPCS_S_CNT_SHIFT)

#define   GEN8_RPCS_SS_CNT_ENABLE		(1 << 11)

#define   GEN8_RPCS_SS_CNT_SHIFT		8

#define   GEN8_RPCS_SS_CNT_MASK			(0x7 << GEN8_RPCS_SS_CNT_SHIFT)

#define   GEN8_RPCS_EU_MAX_SHIFT		4

#define   GEN8_RPCS_EU_MAX_MASK			(0xf << GEN8_RPCS_EU_MAX_SHIFT)

#define   GEN8_RPCS_EU_MIN_SHIFT		0

#define   GEN8_RPCS_EU_MIN_MASK			(0xf << GEN8_RPCS_EU_MIN_SHIFT)



#define RING_RESET_CTL(base)			_MMIO((base) + 0xd0)

#define   RESET_CTL_CAT_ERROR			REG_BIT(2)

#define   RESET_CTL_READY_TO_RESET		REG_BIT(1)

drivers/gpu/drm/i915/gt/intel_sseu.c

+1 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
 */



#include "i915_drv.h"

#include "intel_lrc_reg.h"

#include "intel_engine_regs.h"

#include "intel_sseu.h"



void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,

drivers/gpu/drm/i915/i915_perf.c

+2 −2
Original line number Diff line number Diff line
@@ -2420,7 +2420,7 @@ gen12_configure_all_contexts(struct i915_perf_stream *stream, 
{

	struct flex regs[] = {

		{

			GEN8_R_PWR_CLK_STATE,

			GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),

			CTX_R_PWR_CLK_STATE,

		},

	};
@@ -2440,7 +2440,7 @@ lrc_configure_all_contexts(struct i915_perf_stream *stream, 
#define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)

	struct flex regs[] = {

		{

			GEN8_R_PWR_CLK_STATE,

			GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),

			CTX_R_PWR_CLK_STATE,

		},

		{

drivers/gpu/drm/i915/i915_reg.h

+0 −15
Original line number Diff line number Diff line
@@ -272,21 +272,6 @@ 
#define GEN12_SFC_DONE(n)		_MMIO(0x1cc000 + (n) * 0x1000)

#define GEN12_SFC_DONE_MAX		4



#define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)

#define   GEN8_RPCS_ENABLE		(1 << 31)

#define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)

#define   GEN8_RPCS_S_CNT_SHIFT		15

#define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)

#define   GEN11_RPCS_S_CNT_SHIFT	12

#define   GEN11_RPCS_S_CNT_MASK		(0x3f << GEN11_RPCS_S_CNT_SHIFT)

#define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)

#define   GEN8_RPCS_SS_CNT_SHIFT	8

#define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)

#define   GEN8_RPCS_EU_MAX_SHIFT	4

#define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)

#define   GEN8_RPCS_EU_MIN_SHIFT	0

#define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)



#define WAIT_FOR_RC6_EXIT		_MMIO(0x20CC)

/* HSW only */

#define   HSW_SELECTIVE_READ_ADDRESSING_SHIFT		2