Loading Documentation/admin-guide/sysctl/kernel.rst +0 −17 Original line number Diff line number Diff line Loading @@ -1521,20 +1521,3 @@ is 10 seconds. The softlockup threshold is (``2 * watchdog_thresh``). Setting this tunable to zero will disable lockup detection altogether. uce_kernel_recovery(ARM64 only) =============================== This value can be used to control whether panic the kernel when UCE RAS errors occur in a specific scenario. Each bit controls a scene, 1 means avoid kernel panic when encountering UCE RAS error in this scenario, and 0 means kernel panic. Current usage of each bit: ============ ============== bit0 reserved bit1 reserved bit2 copy_from_user bit3 ~ bit31 reserved ============ ============== arch/arm64/Kconfig +0 −9 Original line number Diff line number Diff line Loading @@ -1647,15 +1647,6 @@ config ARM64_CNP at runtime, and does not affect PEs that do not implement this feature. config ARM64_UCE_KERNEL_RECOVERY bool "arm64 uce kernel recovery for special scenario" depends on ACPI_APEI_SEA help With ARM v8.2 RAS Extension, SEA are usually triggered when memory error are consumed. In some cases, if the error address is in a user page there is a chance to recover. we can isolate this page and killing process instead of die. endmenu menu "ARMv8.3 architectural features" Loading arch/arm64/include/asm/exception.h +0 −13 Original line number Diff line number Diff line Loading @@ -19,19 +19,6 @@ #define __exception_irq_entry __kprobes #endif #ifdef CONFIG_ARM64_UCE_KERNEL_RECOVERY bool arm64_process_kernel_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs, int sig, int code, void __user *siaddr); #else static inline bool arm64_process_kernel_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs, int sig, int code, void __user *siaddr) { return false; } #endif static inline u32 disr_to_esr(u64 disr) { unsigned int esr = ESR_ELx_EC_SERROR << ESR_ELx_EC_SHIFT; Loading arch/arm64/lib/copy_from_user.S +0 −11 Original line number Diff line number Diff line Loading @@ -60,17 +60,6 @@ SYM_FUNC_START(__arch_copy_from_user) #include "copy_template.S" mov x0, #0 // Nothing to copy ret /* * In feature CONFIG_ARM64_UCE_KERNEL_RECOVERY, if RAS error is triggered * in copy_from_user(), RAS error is processed in do_sea() and * copy_from_user_sea_fallback will be assigned to regs->pc, finally return * here to continue processing. */ .global copy_from_user_sea_fallback copy_from_user_sea_fallback: sub x0, end, dst // bytes not copied ret SYM_FUNC_END(__arch_copy_from_user) EXPORT_SYMBOL(__arch_copy_from_user) Loading arch/arm64/mm/Makefile +0 −2 Original line number Diff line number Diff line Loading @@ -11,8 +11,6 @@ obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o obj-$(CONFIG_ARM64_MTE) += mteswap.o KASAN_SANITIZE_physaddr.o += n obj-$(CONFIG_ARM64_UCE_KERNEL_RECOVERY) += uce_kernel_recovery.o obj-$(CONFIG_KASAN) += kasan_init.o KASAN_SANITIZE_kasan_init.o := n Loading Loading
Documentation/admin-guide/sysctl/kernel.rst +0 −17 Original line number Diff line number Diff line Loading @@ -1521,20 +1521,3 @@ is 10 seconds. The softlockup threshold is (``2 * watchdog_thresh``). Setting this tunable to zero will disable lockup detection altogether. uce_kernel_recovery(ARM64 only) =============================== This value can be used to control whether panic the kernel when UCE RAS errors occur in a specific scenario. Each bit controls a scene, 1 means avoid kernel panic when encountering UCE RAS error in this scenario, and 0 means kernel panic. Current usage of each bit: ============ ============== bit0 reserved bit1 reserved bit2 copy_from_user bit3 ~ bit31 reserved ============ ==============
arch/arm64/Kconfig +0 −9 Original line number Diff line number Diff line Loading @@ -1647,15 +1647,6 @@ config ARM64_CNP at runtime, and does not affect PEs that do not implement this feature. config ARM64_UCE_KERNEL_RECOVERY bool "arm64 uce kernel recovery for special scenario" depends on ACPI_APEI_SEA help With ARM v8.2 RAS Extension, SEA are usually triggered when memory error are consumed. In some cases, if the error address is in a user page there is a chance to recover. we can isolate this page and killing process instead of die. endmenu menu "ARMv8.3 architectural features" Loading
arch/arm64/include/asm/exception.h +0 −13 Original line number Diff line number Diff line Loading @@ -19,19 +19,6 @@ #define __exception_irq_entry __kprobes #endif #ifdef CONFIG_ARM64_UCE_KERNEL_RECOVERY bool arm64_process_kernel_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs, int sig, int code, void __user *siaddr); #else static inline bool arm64_process_kernel_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs, int sig, int code, void __user *siaddr) { return false; } #endif static inline u32 disr_to_esr(u64 disr) { unsigned int esr = ESR_ELx_EC_SERROR << ESR_ELx_EC_SHIFT; Loading
arch/arm64/lib/copy_from_user.S +0 −11 Original line number Diff line number Diff line Loading @@ -60,17 +60,6 @@ SYM_FUNC_START(__arch_copy_from_user) #include "copy_template.S" mov x0, #0 // Nothing to copy ret /* * In feature CONFIG_ARM64_UCE_KERNEL_RECOVERY, if RAS error is triggered * in copy_from_user(), RAS error is processed in do_sea() and * copy_from_user_sea_fallback will be assigned to regs->pc, finally return * here to continue processing. */ .global copy_from_user_sea_fallback copy_from_user_sea_fallback: sub x0, end, dst // bytes not copied ret SYM_FUNC_END(__arch_copy_from_user) EXPORT_SYMBOL(__arch_copy_from_user) Loading
arch/arm64/mm/Makefile +0 −2 Original line number Diff line number Diff line Loading @@ -11,8 +11,6 @@ obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o obj-$(CONFIG_ARM64_MTE) += mteswap.o KASAN_SANITIZE_physaddr.o += n obj-$(CONFIG_ARM64_UCE_KERNEL_RECOVERY) += uce_kernel_recovery.o obj-$(CONFIG_KASAN) += kasan_init.o KASAN_SANITIZE_kasan_init.o := n Loading