Commit 7cf03c9f authored by Jason Cooper's avatar Jason Cooper
Browse files

Merge branch 'irqchip/mips' into irqchip/core

parents 55e10798 81ffb18c

arch/mips/ath79/irq.c

+21 −223
Original line number Diff line number Diff line
@@ -26,90 +26,6 @@ 
#include "common.h"

#include "machtypes.h"



static void __init ath79_misc_intc_domain_init(

	struct device_node *node, int irq);



static void ath79_misc_irq_handler(struct irq_desc *desc)

{

	struct irq_domain *domain = irq_desc_get_handler_data(desc);

	void __iomem *base = domain->host_data;

	u32 pending;



	pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &

		  __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);



	if (!pending) {

		spurious_interrupt();

		return;

	}



	while (pending) {

		int bit = __ffs(pending);



		generic_handle_irq(irq_linear_revmap(domain, bit));

		pending &= ~BIT(bit);

	}

}



static void ar71xx_misc_irq_unmask(struct irq_data *d)

{

	void __iomem *base = irq_data_get_irq_chip_data(d);

	unsigned int irq = d->hwirq;

	u32 t;



	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);



	/* flush write */

	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

}



static void ar71xx_misc_irq_mask(struct irq_data *d)

{

	void __iomem *base = irq_data_get_irq_chip_data(d);

	unsigned int irq = d->hwirq;

	u32 t;



	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);



	/* flush write */

	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

}



static void ar724x_misc_irq_ack(struct irq_data *d)

{

	void __iomem *base = irq_data_get_irq_chip_data(d);

	unsigned int irq = d->hwirq;

	u32 t;



	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);

	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);



	/* flush write */

	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);

}



static struct irq_chip ath79_misc_irq_chip = {

	.name		= "MISC",

	.irq_unmask	= ar71xx_misc_irq_unmask,

	.irq_mask	= ar71xx_misc_irq_mask,

};



static void __init ath79_misc_irq_init(void)

{

	if (soc_is_ar71xx() || soc_is_ar913x())

		ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;

	else if (soc_is_ar724x() ||

		 soc_is_ar933x() ||

		 soc_is_ar934x() ||

		 soc_is_qca955x())

		ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;

	else

		BUG();



	ath79_misc_intc_domain_init(NULL, ATH79_CPU_IRQ(6));

}



static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)

{
@@ -212,142 +128,12 @@ static void qca955x_irq_init(void) 
	irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);

}



/*

 * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for

 * these devices typically allocate coherent DMA memory, however the

 * DMA controller may still have some unsynchronized data in the FIFO.

 * Issue a flush in the handlers to ensure that the driver sees

 * the update.

 *

 * This array map the interrupt lines to the DDR write buffer channels.

 */



static unsigned irq_wb_chan[8] = {

	-1, -1, -1, -1, -1, -1, -1, -1,

};



asmlinkage void plat_irq_dispatch(void)

{

	unsigned long pending;

	int irq;



	pending = read_c0_status() & read_c0_cause() & ST0_IM;



	if (!pending) {

		spurious_interrupt();

		return;

	}



	pending >>= CAUSEB_IP;

	while (pending) {

		irq = fls(pending) - 1;

		if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)

			ath79_ddr_wb_flush(irq_wb_chan[irq]);

		do_IRQ(MIPS_CPU_IRQ_BASE + irq);

		pending &= ~BIT(irq);

	}

}



static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)

{

	irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);

	irq_set_chip_data(irq, d->host_data);

	return 0;

}



static const struct irq_domain_ops misc_irq_domain_ops = {

	.xlate = irq_domain_xlate_onecell,

	.map = misc_map,

};



static void __init ath79_misc_intc_domain_init(

	struct device_node *node, int irq)

{

	void __iomem *base = ath79_reset_base;

	struct irq_domain *domain;



	domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT,

			ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, base);

	if (!domain)

		panic("Failed to add MISC irqdomain");



	/* Disable and clear all interrupts */

	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);

	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);



	irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);

}



static int __init ath79_misc_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	int irq;



	irq = irq_of_parse_and_map(node, 0);

	if (!irq)

		panic("Failed to get MISC IRQ");



	ath79_misc_intc_domain_init(node, irq);

	return 0;

}



static int __init ar7100_misc_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;

	return ath79_misc_intc_of_init(node, parent);

}



IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",

		ar7100_misc_intc_of_init);



static int __init ar7240_misc_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;

	return ath79_misc_intc_of_init(node, parent);

}



IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",

		ar7240_misc_intc_of_init);



static int __init ar79_cpu_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	int err, i, count;



	/* Fill the irq_wb_chan table */

	count = of_count_phandle_with_args(

		node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");



	for (i = 0; i < count; i++) {

		struct of_phandle_args args;

		u32 irq = i;



		of_property_read_u32_index(

			node, "qca,ddr-wb-channel-interrupts", i, &irq);

		if (irq >= ARRAY_SIZE(irq_wb_chan))

			continue;



		err = of_parse_phandle_with_args(

			node, "qca,ddr-wb-channels",

			"#qca,ddr-wb-channel-cells",

			i, &args);

		if (err)

			return err;



		irq_wb_chan[irq] = args.args[0];

		pr_info("IRQ: Set flush channel of IRQ%d to %d\n",

			irq, args.args[0]);

	}



	return mips_cpu_irq_of_init(node, parent);

}

IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",

		ar79_cpu_intc_of_init);



void __init arch_init_irq(void)

{

	unsigned irq_wb_chan2 = -1;

	unsigned irq_wb_chan3 = -1;

	bool misc_is_ar71xx;



	if (mips_machtype == ATH79_MACH_GENERIC_OF) {

		irqchip_init();

		return;
@@ -355,14 +141,26 @@ void __init arch_init_irq(void) 


	if (soc_is_ar71xx() || soc_is_ar724x() ||

	    soc_is_ar913x() || soc_is_ar933x()) {

		irq_wb_chan[2] = 3;

		irq_wb_chan[3] = 2;

		irq_wb_chan2 = 3;

		irq_wb_chan3 = 2;

	} else if (soc_is_ar934x()) {

		irq_wb_chan[3] = 2;

		irq_wb_chan3 = 2;

	}



	mips_cpu_irq_init();

	ath79_misc_irq_init();

	ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);



	if (soc_is_ar71xx() || soc_is_ar913x())

		misc_is_ar71xx = true;

	else if (soc_is_ar724x() ||

		 soc_is_ar933x() ||

		 soc_is_ar934x() ||

		 soc_is_qca955x())

		misc_is_ar71xx = false;

	else

		BUG();

	ath79_misc_irq_init(

		ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,

		ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);



	if (soc_is_ar934x())

		ar934x_ip2_irq_init();

arch/mips/include/asm/mach-ath79/ath79.h

+4 −0
Original line number Diff line number Diff line
@@ -144,4 +144,8 @@ static inline u32 ath79_reset_rr(unsigned reg) 
void ath79_device_reset_set(u32 mask);

void ath79_device_reset_clear(u32 mask);



void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);

void ath79_misc_irq_init(void __iomem *regs, int irq,

			int irq_base, bool is_ar71xx);



#endif /* __ASM_MACH_ATH79_H */

drivers/irqchip/Makefile

+2 −0
Original line number Diff line number Diff line 
obj-$(CONFIG_IRQCHIP)			+= irqchip.o



obj-$(CONFIG_ATH79)			+= irq-ath79-cpu.o

obj-$(CONFIG_ATH79)			+= irq-ath79-misc.o

obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o

obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2836.o

obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o

drivers/irqchip/irq-ath79-cpu.c

0 → 100644
+97 −0
Original line number Diff line number Diff line 
/*

 *  Atheros AR71xx/AR724x/AR913x specific interrupt handling

 *

 *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>

 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>

 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>

 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>

 *

 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP

 *

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms of the GNU General Public License version 2 as published

 *  by the Free Software Foundation.

 */



#include <linux/interrupt.h>

#include <linux/irqchip.h>

#include <linux/of.h>



#include <asm/irq_cpu.h>

#include <asm/mach-ath79/ath79.h>



/*

 * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for

 * these devices typically allocate coherent DMA memory, however the

 * DMA controller may still have some unsynchronized data in the FIFO.

 * Issue a flush in the handlers to ensure that the driver sees

 * the update.

 *

 * This array map the interrupt lines to the DDR write buffer channels.

 */



static unsigned irq_wb_chan[8] = {

	-1, -1, -1, -1, -1, -1, -1, -1,

};



asmlinkage void plat_irq_dispatch(void)

{

	unsigned long pending;

	int irq;



	pending = read_c0_status() & read_c0_cause() & ST0_IM;



	if (!pending) {

		spurious_interrupt();

		return;

	}



	pending >>= CAUSEB_IP;

	while (pending) {

		irq = fls(pending) - 1;

		if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)

			ath79_ddr_wb_flush(irq_wb_chan[irq]);

		do_IRQ(MIPS_CPU_IRQ_BASE + irq);

		pending &= ~BIT(irq);

	}

}



static int __init ar79_cpu_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	int err, i, count;



	/* Fill the irq_wb_chan table */

	count = of_count_phandle_with_args(

		node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");



	for (i = 0; i < count; i++) {

		struct of_phandle_args args;

		u32 irq = i;



		of_property_read_u32_index(

			node, "qca,ddr-wb-channel-interrupts", i, &irq);

		if (irq >= ARRAY_SIZE(irq_wb_chan))

			continue;



		err = of_parse_phandle_with_args(

			node, "qca,ddr-wb-channels",

			"#qca,ddr-wb-channel-cells",

			i, &args);

		if (err)

			return err;



		irq_wb_chan[irq] = args.args[0];

	}



	return mips_cpu_irq_of_init(node, parent);

}

IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",

		ar79_cpu_intc_of_init);



void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)

{

	irq_wb_chan[2] = irq_wb_chan2;

	irq_wb_chan[3] = irq_wb_chan3;

	mips_cpu_irq_init();

}

drivers/irqchip/irq-ath79-misc.c

0 → 100644
+189 −0
Original line number Diff line number Diff line 
/*

 *  Atheros AR71xx/AR724x/AR913x MISC interrupt controller

 *

 *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>

 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>

 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>

 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>

 *

 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP

 *

 *  This program is free software; you can redistribute it and/or modify it

 *  under the terms of the GNU General Public License version 2 as published

 *  by the Free Software Foundation.

 */



#include <linux/irqchip.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>



#define AR71XX_RESET_REG_MISC_INT_STATUS	0

#define AR71XX_RESET_REG_MISC_INT_ENABLE	4



#define ATH79_MISC_IRQ_COUNT			32



static void ath79_misc_irq_handler(struct irq_desc *desc)

{

	struct irq_domain *domain = irq_desc_get_handler_data(desc);

	struct irq_chip *chip = irq_desc_get_chip(desc);

	void __iomem *base = domain->host_data;

	u32 pending;



	chained_irq_enter(chip, desc);



	pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &

		  __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);



	if (!pending) {

		spurious_interrupt();

		chained_irq_exit(chip, desc);

		return;

	}



	while (pending) {

		int bit = __ffs(pending);



		generic_handle_irq(irq_linear_revmap(domain, bit));

		pending &= ~BIT(bit);

	}



	chained_irq_exit(chip, desc);

}



static void ar71xx_misc_irq_unmask(struct irq_data *d)

{

	void __iomem *base = irq_data_get_irq_chip_data(d);

	unsigned int irq = d->hwirq;

	u32 t;



	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

	__raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);



	/* flush write */

	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

}



static void ar71xx_misc_irq_mask(struct irq_data *d)

{

	void __iomem *base = irq_data_get_irq_chip_data(d);

	unsigned int irq = d->hwirq;

	u32 t;



	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

	__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);



	/* flush write */

	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

}



static void ar724x_misc_irq_ack(struct irq_data *d)

{

	void __iomem *base = irq_data_get_irq_chip_data(d);

	unsigned int irq = d->hwirq;

	u32 t;



	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);

	__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);



	/* flush write */

	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);

}



static struct irq_chip ath79_misc_irq_chip = {

	.name		= "MISC",

	.irq_unmask	= ar71xx_misc_irq_unmask,

	.irq_mask	= ar71xx_misc_irq_mask,

};



static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)

{

	irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);

	irq_set_chip_data(irq, d->host_data);

	return 0;

}



static const struct irq_domain_ops misc_irq_domain_ops = {

	.xlate = irq_domain_xlate_onecell,

	.map = misc_map,

};



static void __init ath79_misc_intc_domain_init(

	struct irq_domain *domain, int irq)

{

	void __iomem *base = domain->host_data;



	/* Disable and clear all interrupts */

	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);

	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);



	irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);

}



static int __init ath79_misc_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	struct irq_domain *domain;

	void __iomem *base;

	int irq;



	irq = irq_of_parse_and_map(node, 0);

	if (!irq) {

		pr_err("Failed to get MISC IRQ\n");

		return -EINVAL;

	}



	base = of_iomap(node, 0);

	if (!base) {

		pr_err("Failed to get MISC IRQ registers\n");

		return -ENOMEM;

	}



	domain = irq_domain_add_linear(node, ATH79_MISC_IRQ_COUNT,

				&misc_irq_domain_ops, base);

	if (!domain) {

		pr_err("Failed to add MISC irqdomain\n");

		return -EINVAL;

	}



	ath79_misc_intc_domain_init(domain, irq);

	return 0;

}



static int __init ar7100_misc_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;

	return ath79_misc_intc_of_init(node, parent);

}



IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",

		ar7100_misc_intc_of_init);



static int __init ar7240_misc_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;

	return ath79_misc_intc_of_init(node, parent);

}



IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",

		ar7240_misc_intc_of_init);



void __init ath79_misc_irq_init(void __iomem *regs, int irq,

				int irq_base, bool is_ar71xx)

{

	struct irq_domain *domain;



	if (is_ar71xx)

		ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;

	else

		ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;



	domain = irq_domain_add_legacy(NULL, ATH79_MISC_IRQ_COUNT,

			irq_base, 0, &misc_irq_domain_ops, regs);

	if (!domain)

		panic("Failed to create MISC irqdomain");



	ath79_misc_intc_domain_init(domain, irq);

}