Commit 7cbea1b6 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/dg2: Add Wa_14010547955 



This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver really needs
to do is program a chicken bit to reenable some internal behavior.

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarClint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-3-matthew.d.roper@intel.com
parent c0234324

drivers/gpu/drm/i915/display/intel_display.c

+4 −0
Original line number Diff line number Diff line
@@ -991,6 +991,10 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 
	else if (DISPLAY_VER(dev_priv) >= 13)

		tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;



	/* Wa_14010547955:dg2 */

	if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))

		tmp |= DG2_RENDER_CCSTAG_4_3_EN;



	intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);

}

drivers/gpu/drm/i915/i915_reg.h

+3 −2
Original line number Diff line number Diff line
@@ -8483,8 +8483,9 @@ enum { 
							   _PIPEB_CHICKEN)

#define   UNDERRUN_RECOVERY_DISABLE_ADLP	REG_BIT(30)

#define   UNDERRUN_RECOVERY_ENABLE_DG2		REG_BIT(30)

#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)

#define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)

#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU	REG_BIT(15)

#define   DG2_RENDER_CCSTAG_4_3_EN		REG_BIT(12)

#define   PER_PIXEL_ALPHA_BYPASS_EN		REG_BIT(7)









#define FF_MODE2			_MMIO(0x6604)









#define   FF_MODE2_GS_TIMER_MASK	REG_GENMASK(31, 24)