Commit 7c695a2c authored by Lang Yu's avatar Lang Yu Committed by Alex Deucher
Browse files

drm/amdkfd: Remove cu mask from struct queue_properties(v2) 



Actually, cu_mask has been copied to mqd memory and
does't have to persist in queue_properties. Remove it
from queue_properties.

And use struct mqd_update_info to store such properties,
then pass it to update queue operation.

v2:
* Rename pqm_update_queue to pqm_update_queue_properties.
* Rename struct queue_update_info to struct mqd_update_info.
* Rename pqm_set_cu_mask to pqm_update_mqd.

Suggested-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarLang Yu <lang.yu@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c6e559eb

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

+16 −15
Original line number Diff line number Diff line
@@ -405,7 +405,7 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, 


	mutex_lock(&p->mutex);



	retval = pqm_update_queue(&p->pqm, args->queue_id, &properties);

	retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties);



	mutex_unlock(&p->mutex);
@@ -418,7 +418,7 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 
	int retval;

	const int max_num_cus = 1024;

	struct kfd_ioctl_set_cu_mask_args *args = data;

	struct queue_properties properties;

	struct mqd_update_info minfo = {0};

	uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;

	size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
@@ -428,8 +428,8 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 
		return -EINVAL;

	}



	properties.cu_mask_count = args->num_cu_mask;

	if (properties.cu_mask_count == 0) {

	minfo.cu_mask.count = args->num_cu_mask;

	if (minfo.cu_mask.count == 0) {

		pr_debug("CU mask cannot be 0");

		return -EINVAL;

	}
@@ -438,32 +438,33 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 
	 * limit of max_num_cus bits.  We can then just drop any CU mask bits

	 * past max_num_cus bits and just use the first max_num_cus bits.

	 */

	if (properties.cu_mask_count > max_num_cus) {

	if (minfo.cu_mask.count > max_num_cus) {

		pr_debug("CU mask cannot be greater than 1024 bits");

		properties.cu_mask_count = max_num_cus;

		minfo.cu_mask.count = max_num_cus;

		cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);

	}



	properties.cu_mask = kzalloc(cu_mask_size, GFP_KERNEL);

	if (!properties.cu_mask)

	minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL);

	if (!minfo.cu_mask.ptr)

		return -ENOMEM;



	retval = copy_from_user(properties.cu_mask, cu_mask_ptr, cu_mask_size);

	retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size);

	if (retval) {

		pr_debug("Could not copy CU mask from userspace");

		kfree(properties.cu_mask);

		return -EFAULT;

		retval = -EFAULT;

		goto out;

	}



	minfo.update_flag = UPDATE_FLAG_CU_MASK;



	mutex_lock(&p->mutex);



	retval = pqm_set_cu_mask(&p->pqm, args->queue_id, &properties);

	retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo);



	mutex_unlock(&p->mutex);



	if (retval)

		kfree(properties.cu_mask);



out:

	kfree(minfo.cu_mask.ptr);

	return retval;

}

drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c

+0 −1
Original line number Diff line number Diff line
@@ -136,7 +136,6 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_dev *dev, 
	prop.write_ptr = (uint32_t *) kq->wptr_gpu_addr;

	prop.eop_ring_buffer_address = kq->eop_gpu_addr;

	prop.eop_ring_buffer_size = PAGE_SIZE;

	prop.cu_mask = NULL;



	if (init_queue(&kq->queue, &prop) != 0)

		goto err_init_queue;

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c

+5 −4
Original line number Diff line number Diff line
@@ -42,16 +42,17 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) 
}



static void update_cu_mask(struct mqd_manager *mm, void *mqd,

			struct queue_properties *q)

			struct mqd_update_info *minfo)

{

	struct cik_mqd *m;

	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */



	if (q->cu_mask_count == 0)

	if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) ||

	    !minfo->cu_mask.ptr)

		return;



	mqd_symmetrically_map_cu_mask(mm,

		q->cu_mask, q->cu_mask_count, se_mask);

		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);



	m = get_mqd(mqd);

	m->compute_static_thread_mgmt_se0 = se_mask[0];
@@ -215,7 +216,7 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, 
	if (q->format == KFD_QUEUE_FORMAT_AQL)

		m->cp_hqd_pq_control |= NO_UPDATE_RPTR;



	update_cu_mask(mm, mqd, q);

	update_cu_mask(mm, mqd, minfo);

	set_priority(m, q);



	q->is_active = QUEUE_IS_ACTIVE(*q);

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c

+5 −4
Original line number Diff line number Diff line
@@ -42,16 +42,17 @@ static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 
}



static void update_cu_mask(struct mqd_manager *mm, void *mqd,

			   struct queue_properties *q)

			struct mqd_update_info *minfo)

{

	struct v10_compute_mqd *m;

	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */



	if (q->cu_mask_count == 0)

	if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) ||

	    !minfo->cu_mask.ptr)

		return;



	mqd_symmetrically_map_cu_mask(mm,

		q->cu_mask, q->cu_mask_count, se_mask);

		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);



	m = get_mqd(mqd);

	m->compute_static_thread_mgmt_se0 = se_mask[0];
@@ -219,7 +220,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, 
	if (mm->dev->cwsr_enabled)

		m->cp_hqd_ctx_save_control = 0;



	update_cu_mask(mm, mqd, q);

	update_cu_mask(mm, mqd, minfo);

	set_priority(m, q);



	q->is_active = QUEUE_IS_ACTIVE(*q);

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

+5 −4
Original line number Diff line number Diff line
@@ -43,16 +43,17 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 
}



static void update_cu_mask(struct mqd_manager *mm, void *mqd,

			struct queue_properties *q)

			struct mqd_update_info *minfo)

{

	struct v9_mqd *m;

	uint32_t se_mask[KFD_MAX_NUM_SE] = {0};



	if (q->cu_mask_count == 0)

	if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) ||

	    !minfo->cu_mask.ptr)

		return;



	mqd_symmetrically_map_cu_mask(mm,

		q->cu_mask, q->cu_mask_count, se_mask);

		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);



	m = get_mqd(mqd);

	m->compute_static_thread_mgmt_se0 = se_mask[0];
@@ -270,7 +271,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, 
	if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)

		m->cp_hqd_ctx_save_control = 0;



	update_cu_mask(mm, mqd, q);

	update_cu_mask(mm, mqd, minfo);

	set_priority(m, q);



	q->is_active = QUEUE_IS_ACTIVE(*q);