Commit 7c679ef6 authored by Jonathan Kim's avatar Jonathan Kim Committed by Alex Deucher
Browse files

drm/amdgpu: stop resetting xgmi perfmons on disable 



Disabling perf events does not specify reset in ABI so stop doing it in
hardware.

Signed-off-by: default avatarJonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: default avatarHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0f3cd13d

drivers/gpu/drm/amd/amdgpu/amdgpu_df.h

+2 −2
Original line number Diff line number Diff line
@@ -44,9 +44,9 @@ struct amdgpu_df_funcs { 
	void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,

					    bool enable);

	int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,

					 int is_enable);

					 int is_add);

	int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,

					 int is_disable);

					 int is_remove);

	void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,

					 uint64_t *count);

	uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

+14 −9
Original line number Diff line number Diff line
@@ -455,7 +455,8 @@ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev, 
					  uint32_t *lo_base_addr,

					  uint32_t *hi_base_addr,

					  uint32_t *lo_val,

					  uint32_t *hi_val)

					  uint32_t *hi_val,

					  bool is_enable)

{



	uint32_t eventsel, instance, unitmask;
@@ -477,7 +478,8 @@ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev, 
	instance_5432 = (instance >> 2) & 0xf;

	instance_76 = (instance >> 6) & 0x3;



	*lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22);

	*lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel;

	*lo_val = is_enable ? *lo_val | (1 << 22) : *lo_val & ~(1 << 22);

	*hi_val = (instance_76 << 29) | instance_5432;



	DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
@@ -572,14 +574,14 @@ static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev, 
}



static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,

			     int is_enable)

			     int is_add)

{

	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;

	int err = 0, ret = 0;



	switch (adev->asic_type) {

	case CHIP_VEGA20:

		if (is_enable)

		if (is_add)

			return df_v3_6_pmc_add_cntr(adev, config);



		df_v3_6_reset_perfmon_cntr(adev, config);
@@ -589,7 +591,8 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config, 
					&lo_base_addr,

					&hi_base_addr,

					&lo_val,

					&hi_val);

					&hi_val,

					true);



		if (ret)

			return ret;
@@ -612,7 +615,7 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config, 
}



static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,

			    int is_disable)

			    int is_remove)

{

	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;

	int ret = 0;
@@ -624,15 +627,17 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config, 
			&lo_base_addr,

			&hi_base_addr,

			&lo_val,

			&hi_val);

			&hi_val,

			false);



		if (ret)

			return ret;



		df_v3_6_reset_perfmon_cntr(adev, config);



		if (is_disable)

		if (is_remove) {

			df_v3_6_reset_perfmon_cntr(adev, config);

			df_v3_6_pmc_release_cntr(adev, config);

		}



		break;

	default: