Commit 7c5f3d7d authored by Ashish Pawar's avatar Ashish Pawar Committed by Alex Deucher
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drm/amdgpu: PWRBRK sequence changes for Aldebaran 



Modify power brake enablement sequence on Aldebaran

Signed-off-by: default avatarAshish Pawar <ashish.pawar@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6ec598cc

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

+0 −5
Original line number Diff line number Diff line
@@ -782,11 +782,6 @@ void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev) 
	tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);

	WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);



	WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);

	tmp = 0;

	tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1);

	WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp);



	WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);

	tmp = 0;

	tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);