Commit 7c50a3e9 authored by Alan Liu's avatar Alan Liu Committed by Alex Deucher
Browse files

drm/amd/display: Program ACP related register 



- Setup the shift and mask of HDMI_ACP_SEND register
- Program the register in hdmi stream encoder
- Also update ACP register in azalia configuration

Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b3859b16

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

+11 −0
Original line number Diff line number Diff line
@@ -486,6 +486,17 @@ void dce_aud_az_configure( 


	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);



	/*  ACP Data - Supports AI  */

	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA);



	set_reg_field_value(

		value,

		audio_info->flags.info.SUPPORT_AI,

		AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA,

		SUPPORTS_AI);



	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value);



	/*  Audio Descriptors   */

	/* pass through all formats */

	for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

+2 −1
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 
#define DC_LOGGER \

		enc110->base.ctx->logger





#define REG(reg)\

	(enc110->regs->reg)
@@ -635,6 +634,8 @@ static void dce110_stream_encoder_hdmi_set_stream_attribute( 
		HDMI_GC_SEND, 1,

		HDMI_NULL_SEND, 1);



	REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);



	/* following belongs to audio */

	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

+6 −8
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ 
#define SE_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix



#define SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\

#define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\

	SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\

	SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\

	SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
@@ -140,6 +140,7 @@ 
	SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

	SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\

	SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\

	SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\

	SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\

	SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\

	SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
@@ -202,10 +203,7 @@ 
	SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\

	SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)



#define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\

	SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)



#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\

#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\

	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\

	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\

	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
@@ -227,6 +225,7 @@ 
	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\

	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\

	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\

	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\

	SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\

	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
@@ -288,9 +287,6 @@ 
	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\

	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)



#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\

	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)



#define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\

	SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\

	SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
@@ -414,6 +410,7 @@ struct dce_stream_encoder_shift { 
	uint8_t HDMI_GC_SEND;

	uint8_t HDMI_NULL_SEND;

	uint8_t HDMI_DATA_SCRAMBLE_EN;

	uint8_t HDMI_ACP_SEND;

	uint8_t HDMI_AUDIO_INFO_SEND;

	uint8_t AFMT_AUDIO_INFO_UPDATE;

	uint8_t HDMI_AUDIO_INFO_LINE;
@@ -545,6 +542,7 @@ struct dce_stream_encoder_mask { 
	uint32_t HDMI_GC_SEND;

	uint32_t HDMI_NULL_SEND;

	uint32_t HDMI_DATA_SCRAMBLE_EN;

	uint32_t HDMI_ACP_SEND;

	uint32_t HDMI_AUDIO_INFO_SEND;

	uint32_t AFMT_AUDIO_INFO_UPDATE;

	uint32_t HDMI_AUDIO_INFO_LINE;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

+2 −1
Original line number Diff line number Diff line
@@ -37,7 +37,6 @@ 
#define DC_LOGGER \

		enc1->base.ctx->logger





#define REG(reg)\

	(enc1->regs->reg)
@@ -597,6 +596,8 @@ void enc1_stream_encoder_hdmi_set_stream_attribute( 
		HDMI_GC_SEND, 1,

		HDMI_NULL_SEND, 1);



	REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);



	/* following belongs to audio */

	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

+2 −14
Original line number Diff line number Diff line
@@ -194,7 +194,7 @@ struct dcn10_stream_enc_registers { 
#define SE_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix



#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\

#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\

	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\

	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\

	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
@@ -211,6 +211,7 @@ struct dcn10_stream_enc_registers { 
	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\

	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\

	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\

	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\

	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\

	SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\

	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
@@ -339,15 +340,6 @@ struct dcn10_stream_enc_registers { 
	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\

	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)



#if defined(CONFIG_DRM_AMD_DC_HDCP)

#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\

	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh),\

	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh)

#else

#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\

	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)

#endif



#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\

	SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\

	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
@@ -586,9 +578,7 @@ struct dcn10_stream_enc_registers { 


struct dcn10_stream_encoder_shift {

	SE_REG_FIELD_LIST_DCN1_0(uint8_t);

#if defined(CONFIG_DRM_AMD_DC_HDCP)

	uint8_t HDMI_ACP_SEND;

#endif

	SE_REG_FIELD_LIST_DCN2_0(uint8_t);

	SE_REG_FIELD_LIST_DCN3_0(uint8_t);

	SE_REG_FIELD_LIST_DCN3_2(uint8_t);
@@ -597,9 +587,7 @@ struct dcn10_stream_encoder_shift { 


struct dcn10_stream_encoder_mask {

	SE_REG_FIELD_LIST_DCN1_0(uint32_t);

#if defined(CONFIG_DRM_AMD_DC_HDCP)

	uint32_t HDMI_ACP_SEND;

#endif

	SE_REG_FIELD_LIST_DCN2_0(uint32_t);

	SE_REG_FIELD_LIST_DCN3_0(uint32_t);

	SE_REG_FIELD_LIST_DCN3_2(uint32_t);