Commit 7c300735 authored by Horatiu Vultur's avatar Horatiu Vultur Committed by David S. Miller
Browse files

net: lan966x: Add registers used to configure lag interfaces 



Add the registers used by lan966x to configure the lag interface.

Signed-off-by: default avatarHoratiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e46c5b8e

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

+45 −0
Original line number Diff line number Diff line
@@ -363,6 +363,51 @@ enum lan966x_target { 
#define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\

	FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x)



/*      ANA:COMMON:AGGR_CFG */

#define ANA_AGGR_CFG              __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 0, 0, 1, 4)



#define ANA_AGGR_CFG_AC_RND_ENA                  BIT(6)

#define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\

	FIELD_PREP(ANA_AGGR_CFG_AC_RND_ENA, x)

#define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\

	FIELD_GET(ANA_AGGR_CFG_AC_RND_ENA, x)



#define ANA_AGGR_CFG_AC_DMAC_ENA                 BIT(5)

#define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\

	FIELD_PREP(ANA_AGGR_CFG_AC_DMAC_ENA, x)

#define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\

	FIELD_GET(ANA_AGGR_CFG_AC_DMAC_ENA, x)



#define ANA_AGGR_CFG_AC_SMAC_ENA                 BIT(4)

#define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\

	FIELD_PREP(ANA_AGGR_CFG_AC_SMAC_ENA, x)

#define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\

	FIELD_GET(ANA_AGGR_CFG_AC_SMAC_ENA, x)



#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA         BIT(3)

#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\

	FIELD_PREP(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x)

#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\

	FIELD_GET(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x)



#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA           BIT(2)

#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\

	FIELD_PREP(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x)

#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\

	FIELD_GET(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x)



#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA           BIT(1)

#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\

	FIELD_PREP(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x)

#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\

	FIELD_GET(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x)



#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA           BIT(0)

#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\

	FIELD_PREP(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x)

#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\

	FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x)



/*      CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */

#define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4)