drm/amdgpu: update golden setting/tiling table of tahiti (7c0a705e) · Commits · EulixOS / Software / Kernel

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+198 −146

Original line number	Original line	Diff line number	Diff line
	@@ -656,239 +656,291 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
	} else if ((adev->asic_type == CHIP_TAHITI) \|\| (adev->asic_type == CHIP_PITCAIRN)) {		} else if ((adev->asic_type == CHIP_TAHITI) \|\| (adev->asic_type == CHIP_PITCAIRN)) {
	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
	switch (reg_offset) {		switch (reg_offset) {
	case 0: /* non-AA compressed depth or any compressed stencil */		case 0:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) \|
			NUM_BANKS(ADDR_SURF_16_BANK));
	break;		break;
	case 1: /* 2xAA/4xAA compressed depth only */		case 1:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) \|
			NUM_BANKS(ADDR_SURF_16_BANK));
	break;		break;
	case 2: /* 8xAA compressed depth only */		case 2:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) \|
			NUM_BANKS(ADDR_SURF_16_BANK));
	break;		break;
	case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */		case 3:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_4_BANK) \|
			TILE_SPLIT(split_equal_to_row_size));
	break;		break;
	case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */		case 4:
	gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|		ARRAY_MODE(ARRAY_1D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
	break;		break;
	case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */		case 5:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(split_equal_to_row_size) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
	break;		break;
	case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */		case 6:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(split_equal_to_row_size) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
	break;		break;
	case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */		case 7:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
	TILE_SPLIT(split_equal_to_row_size) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
	break;		break;
	case 8: /* 1D and 1D Array Surfaces */		case 8:
	gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) \|		gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
	MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
	break;		break;
	case 9: /* Displayable maps. */		case 9:
	gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|		ARRAY_MODE(ARRAY_1D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
	break;		break;
	case 10: /* Display 8bpp. */		case 10:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) \|
			NUM_BANKS(ADDR_SURF_16_BANK));
	break;		break;
	case 11: /* Display 16bpp. */		case 11:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) \|
			NUM_BANKS(ADDR_SURF_16_BANK));
	break;		break;
	case 12: /* Display 32bpp. */		case 12:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_16_BANK));
	break;		break;
	case 13: /* Thin. */		case 13:
	gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_1D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
	break;		break;
	case 14: /* Thin 8 bpp. */		case 14:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_16_BANK));
	break;		break;
	case 15: /* Thin 16 bpp. */		case 15:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_16_BANK));
	break;		break;
	case 16: /* Thin 32 bpp. */		case 16:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_16_BANK));
	break;		break;
	case 17: /* Thin 64 bpp. */		case 17:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(split_equal_to_row_size) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
			BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
			MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|		NUM_BANKS(ADDR_SURF_16_BANK) \|
			TILE_SPLIT(split_equal_to_row_size));
			break;
			case 18:
			gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
			ARRAY_MODE(ARRAY_1D_TILED_THICK) \|
			PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16));
			break;
			case 19:
			gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
			ARRAY_MODE(ARRAY_2D_TILED_XTHICK) \|
			PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_16_BANK) \|
			TILE_SPLIT(split_equal_to_row_size));
	break;		break;
	case 21: /* 8 bpp PRT. */		case 20:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THICK) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
			BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|
			MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|		NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) \|		TILE_SPLIT(split_equal_to_row_size));
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
	break;		break;
	case 22: /* 16 bpp PRT */		case 21:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
			PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
			TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
			BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
			BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) \|
			MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_4_BANK));
			break;
			case 22:
			gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
			ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_4_BANK));
	break;		break;
	case 23: /* 32 bpp PRT */		case 23:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
	break;		break;
	case 24: /* 64 bpp PRT */		case 24:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) \|
	NUM_BANKS(ADDR_SURF_16_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
	break;		break;
	case 25: /* 128 bpp PRT */		case 25:
	gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
	MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|		ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
	PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) \|		PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
	TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) \|		TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) \|
	NUM_BANKS(ADDR_SURF_8_BANK) \|
	BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|		BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
	BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) \|		BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
	MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));		MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
	break;		break;
	default:		case 26:
	gb_tile_moden = 0;		gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
			ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
			PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
			TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) \|
			BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
			BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
			MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
			break;
			case 27:
			gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
			ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
			PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
			TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) \|
			BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
			BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
			MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
	break;		break;
			case 28:
			gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
			ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
			PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
			TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) \|
			BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
			BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
			MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
			break;
			case 29:
			gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
			ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
			PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
			TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) \|
			BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
			BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) \|
			MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
			break;
			case 30:
			gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) \|
			ARRAY_MODE(ARRAY_2D_TILED_THIN1) \|
			PIPE_CONFIG(ADDR_SURF_P4_8x16) \|
			TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) \|
			BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) \|
			BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) \|
			MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) \|
			NUM_BANKS(ADDR_SURF_2_BANK));
			break;
			default:
			continue;
	}		}
	adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;		adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
	WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);		WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);

drivers/gpu/drm/amd/amdgpu/si.c

+23 −15

Original line number	Original line	Diff line number	Diff line
	@@ -43,13 +43,14 @@

	static const u32 tahiti_golden_registers[] =		static const u32 tahiti_golden_registers[] =
	{		{
			0x17bc, 0x00000030, 0x00000011,
	0x2684, 0x00010000, 0x00018208,		0x2684, 0x00010000, 0x00018208,
	0x260c, 0xffffffff, 0x00000000,		0x260c, 0xffffffff, 0x00000000,
	0x260d, 0xf00fffff, 0x00000400,		0x260d, 0xf00fffff, 0x00000400,
	0x260e, 0x0002021c, 0x00020200,		0x260e, 0x0002021c, 0x00020200,
	0x031e, 0x00000080, 0x00000000,		0x031e, 0x00000080, 0x00000000,
	0x340c, 0x000300c0, 0x00800040,		0x340c, 0x000000c0, 0x00800040,
	0x360c, 0x000300c0, 0x00800040,		0x360c, 0x000000c0, 0x00800040,
	0x16ec, 0x000000f0, 0x00000070,		0x16ec, 0x000000f0, 0x00000070,
	0x16f0, 0x00200000, 0x50100000,		0x16f0, 0x00200000, 0x50100000,
	0x1c0c, 0x31000311, 0x00000011,		0x1c0c, 0x31000311, 0x00000011,
	@@ -60,7 +61,7 @@ static const u32 tahiti_golden_registers[] =
	0x22c4, 0x0000ff0f, 0x00000000,		0x22c4, 0x0000ff0f, 0x00000000,
	0xa293, 0x07ffffff, 0x4e000000,		0xa293, 0x07ffffff, 0x4e000000,
	0xa0d4, 0x3f3f3fff, 0x2a00126a,		0xa0d4, 0x3f3f3fff, 0x2a00126a,
	0x000c, 0x000000ff, 0x0040,		0x000c, 0xffffffff, 0x0040,
	0x000d, 0x00000040, 0x00004040,		0x000d, 0x00000040, 0x00004040,
	0x2440, 0x07ffffff, 0x03000000,		0x2440, 0x07ffffff, 0x03000000,
	0x23a2, 0x01ff1f3f, 0x00000000,		0x23a2, 0x01ff1f3f, 0x00000000,
	@@ -73,7 +74,11 @@ static const u32 tahiti_golden_registers[] =
	0x2234, 0xffffffff, 0x000fff40,		0x2234, 0xffffffff, 0x000fff40,
	0x2235, 0x0000001f, 0x00000010,		0x2235, 0x0000001f, 0x00000010,
	0x0504, 0x20000000, 0x20fffed8,		0x0504, 0x20000000, 0x20fffed8,
	0x0570, 0x000c0fc0, 0x000c0400		0x0570, 0x000c0fc0, 0x000c0400,
			0x052c, 0x0fffffff, 0xffffffff,
			0x052d, 0x0fffffff, 0x0fffffff,
			0x052e, 0x0fffffff, 0x0fffffff,
			0x052f, 0x0fffffff, 0x0fffffff
	};		};

	static const u32 tahiti_golden_registers2[] =		static const u32 tahiti_golden_registers2[] =
	@@ -83,12 +88,13 @@ static const u32 tahiti_golden_registers2[] =

	static const u32 tahiti_golden_rlc_registers[] =		static const u32 tahiti_golden_rlc_registers[] =
	{		{
			0x263e, 0xffffffff, 0x12011003,
	0x3109, 0xffffffff, 0x00601005,		0x3109, 0xffffffff, 0x00601005,
	0x311f, 0xffffffff, 0x10104040,		0x311f, 0xffffffff, 0x10104040,
	0x3122, 0xffffffff, 0x0100000a,		0x3122, 0xffffffff, 0x0100000a,
	0x30c5, 0xffffffff, 0x00000800,		0x30c5, 0xffffffff, 0x00000800,
	0x30c3, 0xffffffff, 0x800000f4,		0x30c3, 0xffffffff, 0x800000f4,
	0x3d2a, 0xffffffff, 0x00000000		0x3d2a, 0x00000008, 0x00000000
	};		};

	static const u32 pitcairn_golden_registers[] =		static const u32 pitcairn_golden_registers[] =
	@@ -513,18 +519,18 @@ static const u32 tahiti_mgcg_cgcg_init[] =
	0x21c2, 0xffffffff, 0x00900100,		0x21c2, 0xffffffff, 0x00900100,
	0x311e, 0xffffffff, 0x00000080,		0x311e, 0xffffffff, 0x00000080,
	0x3101, 0xffffffff, 0x0020003f,		0x3101, 0xffffffff, 0x0020003f,
	0xc, 0xffffffff, 0x0000001c,		0x000c, 0xffffffff, 0x0000001c,
	0xd, 0x000f0000, 0x000f0000,		0x000d, 0x000f0000, 0x000f0000,
	0x583, 0xffffffff, 0x00000100,		0x0583, 0xffffffff, 0x00000100,
	0x409, 0xffffffff, 0x00000100,		0x0409, 0xffffffff, 0x00000100,
	0x40b, 0x00000101, 0x00000000,		0x040b, 0x00000101, 0x00000000,
	0x82a, 0xffffffff, 0x00000104,		0x082a, 0xffffffff, 0x00000104,
	0x993, 0x000c0000, 0x000c0000,		0x0993, 0x000c0000, 0x000c0000,
	0x992, 0x000c0000, 0x000c0000,		0x0992, 0x000c0000, 0x000c0000,
	0x1579, 0xff000fff, 0x00000100,		0x1579, 0xff000fff, 0x00000100,
	0x157a, 0x00000001, 0x00000001,		0x157a, 0x00000001, 0x00000001,
	0xbd4, 0x00000001, 0x00000001,		0x0bd4, 0x00000001, 0x00000001,
	0xc33, 0xc0000fff, 0x00000104,		0x0c33, 0xc0000fff, 0x00000104,
	0x3079, 0x00000001, 0x00000001,		0x3079, 0x00000001, 0x00000001,
	0x3430, 0xfffffff0, 0x00000100,		0x3430, 0xfffffff0, 0x00000100,
	0x3630, 0xfffffff0, 0x00000100		0x3630, 0xfffffff0, 0x00000100
	@@ -1179,6 +1185,8 @@ static int si_common_early_init(void *handle)
	AMD_CG_SUPPORT_HDP_LS \|		AMD_CG_SUPPORT_HDP_LS \|
	AMD_CG_SUPPORT_HDP_MGCG;		AMD_CG_SUPPORT_HDP_MGCG;
	adev->pg_flags = 0;		adev->pg_flags = 0;
			adev->external_rev_id = (adev->rev_id == 0) ? 1 :
			(adev->rev_id == 1) ? 5 : 6;
	break;		break;
	case CHIP_PITCAIRN:		case CHIP_PITCAIRN:
	adev->cg_flags =		adev->cg_flags =