Commit 7c0849c7 authored by Hao Chen's avatar Hao Chen Committed by Zheng Zengkai
Browse files

net: hns3: PF supports to set and query lane_num by sysfs 

driver inclusion
category:feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I62HX2



----------------------------------------------------------------------

When serdes lane support setting 25Gb/s、50Gb/s speed and user wants to
set port speed as 50Gb/s, it can be setted as one 50Gb/s serdes lane or
two 25Gb/s serdes lanes.

So, this patch adds support to query and set lane number by sysfs
to satisfy this scenario.

Signed-off-by: default avatarHao Chen <chenhao418@huawei.com>
Signed-off-by: default avatarJiantao Xiao <xiaojiantao1@h-partners.com>
Reviewed-by: default avatarYue Haibing <yuehaibing@huawei.com>
Reviewed-by: default avatarJian Shen <shenjian15@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent b66ae5ce

drivers/net/ethernet/hisilicon/hns3/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ hclgevf-objs = hns3vf/hclgevf_main.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlin 
		hns3_common/hclge_comm_cmd.o hns3_common/hclge_comm_rss.o hns3_common/hclge_comm_tqp_stats.o



obj-$(CONFIG_HNS3_HCLGE) += hclge.o

hclge-objs = hns3pf/hclge_main.o hns3pf/hclge_mdio.o hns3pf/hclge_tm.o \

hclge-objs = hns3pf/hclge_main.o hns3pf/hclge_mdio.o hns3pf/hclge_tm.o hns3pf/hclge_sysfs.o \

		hns3pf/hclge_mbx.o hns3pf/hclge_err.o  hns3pf/hclge_debugfs.o hns3pf/hclge_ptp.o hns3pf/hclge_devlink.o \

		hns3_common/hclge_comm_cmd.o hns3_common/hclge_comm_rss.o hns3_common/hclge_comm_tqp_stats.o

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+4 −0
Original line number Diff line number Diff line
@@ -100,6 +100,7 @@ enum HNAE3_DEV_CAP_BITS { 
	HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,

	HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,

	HNAE3_DEV_SUPPORT_CQ_B,

	HNAE3_DEV_SUPPORT_LANE_NUM_B,

};



#define hnae3_ae_dev_fd_supported(ae_dev) \
@@ -162,6 +163,9 @@ enum HNAE3_DEV_CAP_BITS { 
#define hnae3_ae_dev_cq_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)



#define hnae3_ae_dev_lane_num_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)



enum HNAE3_PF_CAP_BITS {

	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,

};

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

+1 −0
Original line number Diff line number Diff line
@@ -153,6 +153,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = { 
	{HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},

	{HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},

	{HCLGE_COMM_CAP_FD_B, HNAE3_DEV_SUPPORT_FD_B},

	{HCLGE_COMM_CAP_LANE_NUM_B, HNAE3_DEV_SUPPORT_LANE_NUM_B},

};



static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+1 −0
Original line number Diff line number Diff line
@@ -342,6 +342,7 @@ enum HCLGE_COMM_CAP_BITS { 
	HCLGE_COMM_CAP_CQ_B = 18,

	HCLGE_COMM_CAP_GRO_B = 20,

	HCLGE_COMM_CAP_FD_B = 21,

	HCLGE_COMM_CAP_LANE_NUM_B = 27,

};



enum HCLGE_COMM_API_CAP_BITS {

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+5 −2
Original line number Diff line number Diff line
@@ -322,7 +322,9 @@ struct hclge_config_mac_speed_dup_cmd { 


#define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B	0

	u8 mac_change_fec_en;

	u8 rsv[22];

	u8 rsv[4];

	u8 lane_num;

	u8 rsv1[17];

};



#define HCLGE_TQP_ENABLE_B		0
@@ -349,7 +351,8 @@ struct hclge_sfp_info_cmd { 
	__le32 speed_ability; /* speed ability for current media */

	__le32 module_type;

	u8 fec_ability;

	u8 rsv[7];

	u8 lane_num;

	u8 rsv[6];

};



#define HCLGE_MAC_CFG_FEC_AUTO_EN_B	0