Commit 7c05d3d0 authored by Veerasenareddy Burru's avatar Veerasenareddy Burru Committed by David S. Miller
Browse files

octeon_ep: control mailbox for multiple PFs 



Add control mailbox support for multiple PFs.
Update control mbox base address calculation based on PF function link.

Signed-off-by: default avatarVeerasenareddy Burru <vburru@marvell.com>
Signed-off-by: default avatarAbhijit Ayarekar <aayarekar@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 24d43332

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

+15 −1
Original line number Diff line number Diff line
@@ -13,6 +13,9 @@ 
#include "octep_main.h"

#include "octep_regs_cn9k_pf.h"



#define CTRL_MBOX_MAX_PF	128

#define CTRL_MBOX_SZ		((size_t)(0x400000 / CTRL_MBOX_MAX_PF))



/* Names of Hardware non-queue generic interrupts */

static char *cn93_non_ioq_msix_names[] = {

	"epf_ire_rint",
@@ -198,7 +201,9 @@ static void octep_init_config_cn93_pf(struct octep_device *oct) 
{

	struct octep_config *conf = oct->conf;

	struct pci_dev *pdev = oct->pdev;

	u8 link = 0;

	u64 val;

	int pos;



	/* Read ring configuration:

	 * PF ring count, number of VFs and rings per VF supported
@@ -234,7 +239,16 @@ static void octep_init_config_cn93_pf(struct octep_device *oct) 
	conf->msix_cfg.ioq_msix = conf->pf_ring_cfg.active_io_rings;

	conf->msix_cfg.non_ioq_msix_names = cn93_non_ioq_msix_names;



	conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr + (0x400000ull * 7);

	pos = pci_find_ext_capability(oct->pdev, PCI_EXT_CAP_ID_SRIOV);

	if (pos) {

		pci_read_config_byte(oct->pdev,

				     pos + PCI_SRIOV_FUNC_LINK,

				     &link);

		link = PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link);

	}

	conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr +

					   (0x400000ull * 7) +

					   (link * CTRL_MBOX_SZ);

}



/* Setup registers for a hardware Tx Queue  */