Commit 7bf2dd59 authored by Kan Liang's avatar Kan Liang Committed by Yunying Sun
Browse files

perf/x86/intel: Apply the common initialization code for ADL 

mainline inclusion
from mainline-v6.10-rc1
commit 299a5fc8e783eed705015e83e381912dbbf3eabc
category: bugfix
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IAGLFT
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=299a5fc8e783eed705015e83e381912dbbf3eabc



-------------------------------------

Use the intel_pmu_init_glc() and intel_pmu_init_grt() to replace the
duplicate code for ADL.

The current code already checks the PERF_X86_EVENT_TOPDOWN flag before
invoking the Topdown metrics functions. (The PERF_X86_EVENT_TOPDOWN flag
is to indicate the Topdown metric feature, which is only available for
the p-core.) Drop the unnecessary adl_set_topdown_event_period() and
adl_update_topdown_event().

Intel-SIG: commit 299a5fc8e783 perf/x86/intel: Apply the common initialization code for ADL
Backport as a dependency needed by the GNR distinct pmu name fix

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20230829125806.3016082-5-kan.liang@linux.intel.com


Signed-off-by: default avatarYunying Sun <yunying.sun@intel.com>
parent c8eefc43

arch/x86/events/intel/core.c

+2 −51
Original line number Diff line number Diff line
@@ -2561,16 +2561,6 @@ static int icl_set_topdown_event_period(struct perf_event *event) 
	return 0;

}



static int adl_set_topdown_event_period(struct perf_event *event)

{

	struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);



	if (pmu->cpu_type != hybrid_big)

		return 0;



	return icl_set_topdown_event_period(event);

}



DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);



static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
@@ -2713,16 +2703,6 @@ static u64 icl_update_topdown_event(struct perf_event *event) 
						 x86_pmu.num_topdown_events - 1);

}



static u64 adl_update_topdown_event(struct perf_event *event)

{

	struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);



	if (pmu->cpu_type != hybrid_big)

		return 0;



	return icl_update_topdown_event(event);

}



DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update);



static void intel_pmu_read_topdown_event(struct perf_event *event)
@@ -6716,32 +6696,11 @@ __init int intel_pmu_init(void) 
		static_branch_enable(&perf_is_hybrid);

		x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS;



		x86_pmu.pebs_aliases = NULL;

		x86_pmu.pebs_prec_dist = true;

		x86_pmu.pebs_block = true;

		x86_pmu.flags |= PMU_FL_HAS_RSP_1;

		x86_pmu.flags |= PMU_FL_NO_HT_SHARING;

		x86_pmu.flags |= PMU_FL_INSTR_LATENCY;

		x86_pmu.lbr_pt_coexist = true;

		x86_pmu.pebs_latency_data = adl_latency_data_small;

		x86_pmu.num_topdown_events = 8;

		static_call_update(intel_pmu_update_topdown_event,

				   &adl_update_topdown_event);

		static_call_update(intel_pmu_set_topdown_event_period,

				   &adl_set_topdown_event_period);



		x86_pmu.filter = intel_pmu_filter;

		x86_pmu.get_event_constraints = adl_get_event_constraints;

		x86_pmu.hw_config = adl_hw_config;

		x86_pmu.limit_period = glc_limit_period;

		x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;

		/*

		 * The rtm_abort_event is used to check whether to enable GPRs

		 * for the RTM abort event. Atom doesn't have the RTM abort

		 * event. There is no harmful to set it in the common

		 * x86_pmu.rtm_abort_event.

		 */

		x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);



		td_attr = adl_hybrid_events_attrs;

		mem_attr = adl_hybrid_mem_attrs;
@@ -6753,6 +6712,7 @@ __init int intel_pmu_init(void) 
		pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];

		pmu->name = "cpu_core";

		pmu->cpu_type = hybrid_big;

		intel_pmu_init_glc(&pmu->pmu);

		pmu->late_ack = true;

		if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {

			pmu->num_counters = x86_pmu.num_counters + 2;
@@ -6782,16 +6742,13 @@ __init int intel_pmu_init(void) 
		pmu->intel_cap.perf_metrics = 1;

		pmu->intel_cap.pebs_output_pt_available = 0;



		memcpy(pmu->hw_cache_event_ids, glc_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));

		memcpy(pmu->hw_cache_extra_regs, glc_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));

		pmu->event_constraints = intel_glc_event_constraints;

		pmu->pebs_constraints = intel_glc_pebs_event_constraints;

		pmu->extra_regs = intel_glc_extra_regs;



		/* Initialize Atom core specific PerfMon capabilities.*/

		pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];

		pmu->name = "cpu_atom";

		pmu->cpu_type = hybrid_small;

		intel_pmu_init_grt(&pmu->pmu);

		pmu->mid_ack = true;

		pmu->num_counters = x86_pmu.num_counters;

		pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
@@ -6803,12 +6760,6 @@ __init int intel_pmu_init(void) 
		pmu->intel_cap.perf_metrics = 0;

		pmu->intel_cap.pebs_output_pt_available = 1;



		memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));

		memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));

		pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;

		pmu->event_constraints = intel_slm_event_constraints;

		pmu->pebs_constraints = intel_grt_pebs_event_constraints;

		pmu->extra_regs = intel_grt_extra_regs;

		if (is_mtl(boot_cpu_data.x86_model)) {

			x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].extra_regs = intel_rwc_extra_regs;

			x86_pmu.pebs_latency_data = mtl_latency_data_small;