Commit 7ba79a67 authored by Vinay Belgaumkar's avatar Vinay Belgaumkar Committed by John Harrison
Browse files

drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled 



Also ensure uc_init is called before we initialize RPS so that we
can check for SLPC support. We do not need to enable up/down
interrupts when SLPC is enabled. However, we still need the ARAT
interrupt, which will be enabled separately later.

v2: Explicitly return from intel_rps_enable with slpc check (Matthew B)

Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Signed-off-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: default avatarSundaresan Sujaritha <sujaritha.sundaresan@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-3-vinay.belgaumkar@intel.com
parent dff0fc49

drivers/gpu/drm/i915/gt/intel_gt.c

+1 −1
Original line number Diff line number Diff line
@@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) 
	intel_gt_init_timelines(gt);

	intel_gt_pm_init_early(gt);



	intel_rps_init_early(&gt->rps);

	intel_uc_init_early(&gt->uc);

	intel_rps_init_early(&gt->rps);

}



int intel_gt_probe_lmem(struct intel_gt *gt)

drivers/gpu/drm/i915/gt/intel_rps.c

+23 −0
Original line number Diff line number Diff line
@@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) 
	return rps_to_gt(rps)->uncore;

}



static bool rps_uses_slpc(struct intel_rps *rps)

{

	struct intel_gt *gt = rps_to_gt(rps);



	return intel_uc_uses_guc_slpc(&gt->uc);

}



static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask)

{

	return mask & ~rps->pm_intrmsk_mbz;
@@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps *rps) 
{

	struct intel_gt *gt = rps_to_gt(rps);



	GEM_BUG_ON(rps_uses_slpc(rps));



	GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",

		 rps->pm_events, rps_pm_mask(rps, rps->last_freq));
@@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val) 
	struct drm_i915_private *i915 = rps_to_i915(rps);

	u32 swreq;



	GEM_BUG_ON(rps_uses_slpc(rps));



	if (GRAPHICS_VER(i915) >= 9)

		swreq = GEN9_FREQUENCY(val);

	else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
@@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps) 
{

	int adj;



	if (!intel_rps_is_enabled(rps))

		return;



	GEM_BUG_ON(atomic_read(&rps->num_waiters));



	if (!intel_rps_clear_active(rps))
@@ -1356,6 +1370,9 @@ void intel_rps_enable(struct intel_rps *rps) 
	if (!HAS_RPS(i915))

		return;



	if (rps_uses_slpc(rps))

		return;



	intel_gt_check_clock_frequency(rps_to_gt(rps));



	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
@@ -1829,6 +1846,9 @@ void intel_rps_init(struct intel_rps *rps) 
{

	struct drm_i915_private *i915 = rps_to_i915(rps);



	if (rps_uses_slpc(rps))

		return;



	if (IS_CHERRYVIEW(i915))

		chv_rps_init(rps);

	else if (IS_VALLEYVIEW(i915))
@@ -1885,6 +1905,9 @@ void intel_rps_init(struct intel_rps *rps) 


void intel_rps_sanitize(struct intel_rps *rps)

{

	if (rps_uses_slpc(rps))

		return;



	if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)

		rps_disable_interrupts(rps);

}