Unverified Commit 7ba63521 authored Oct 06, 2022 by Tharun Kumar P Committed by Mark Brown Nov 29, 2022

spi: microchip: pci1xxxx: Add suspend and resume support for PCI1XXXX SPI driver



Implement suspend, resume callbacks, store config at suspend and restore
config at time of resume

Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
Link: https://lore.kernel.org/r/20221006050514.115564-3-tharunkumar.pasumarthi@microchip.com


Signed-off-by: Mark Brown <broonie@kernel.org>

parent c771b4ea

drivers/spi/spi-pci1xxxx.c

+78 −0

Original line number	Diff line number	Diff line
		@@ -57,6 +57,9 @@
		#define SPI_CHIP_SEL_COUNT 7
		#define VENDOR_ID_MCHP 0x1055

		#define SPI_SUSPEND_CONFIG 0x101
		#define SPI_RESUME_CONFIG 0x303

		struct pci1xxxx_spi_internal {
		u8 hw_inst;
		bool spi_xfer_in_progress;
		@@ -383,10 +386,85 @@ static int pci1xxxx_spi_probe(struct pci_dev pdev, const struct pci_device_id
		return ret;
		}

		static void store_restore_config(struct pci1xxxx_spi *spi_ptr,
		struct pci1xxxx_spi_internal *spi_sub_ptr,
		u8 inst, bool store)
		{
		u32 regval;

		if (store) {
		regval = readl(spi_ptr->reg_base +
		SPI_MST_CTL_REG_OFFSET(spi_sub_ptr->hw_inst));
		regval &= SPI_MST_CTL_DEVSEL_MASK;
		spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7;
		regval = readl(spi_ptr->reg_base +
		SPI_PCI_CTRL_REG_OFFSET(spi_sub_ptr->hw_inst));
		regval &= SPI_MSI_VECTOR_SEL_MASK;
		spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1;
		} else {
		regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
		regval &= ~SPI_MST_CTL_DEVSEL_MASK;
		regval \|= (spi_sub_ptr->prev_val.dev_sel << 25);
		writel(regval,
		spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
		writel((spi_sub_ptr->prev_val.msi_vector_sel << 4),
		spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst));
		}
		}

		static int pci1xxxx_spi_resume(struct device *dev)
		{
		struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
		struct pci1xxxx_spi_internal *spi_sub_ptr;
		u32 regval = SPI_RESUME_CONFIG;
		u8 iter;

		for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
		spi_sub_ptr = spi_ptr->spi_int[iter];
		spi_master_resume(spi_sub_ptr->spi_host);
		writel(regval, spi_ptr->reg_base +
		SPI_MST_EVENT_MASK_REG_OFFSET(iter));

		/* Restore config at resume */
		store_restore_config(spi_ptr, spi_sub_ptr, iter, 0);
		}

		return 0;
		}

		static int pci1xxxx_spi_suspend(struct device *dev)
		{
		struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
		struct pci1xxxx_spi_internal *spi_sub_ptr;
		u32 reg1 = SPI_SUSPEND_CONFIG;
		u8 iter;

		for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
		spi_sub_ptr = spi_ptr->spi_int[iter];

		while (spi_sub_ptr->spi_xfer_in_progress)
		msleep(20);

		/* Store existing config before suspend */
		store_restore_config(spi_ptr, spi_sub_ptr, iter, 1);
		spi_master_suspend(spi_sub_ptr->spi_host);
		writel(reg1, spi_ptr->reg_base +
		SPI_MST_EVENT_MASK_REG_OFFSET(iter));
		}

		return 0;
		}

		static DEFINE_SIMPLE_DEV_PM_OPS(spi_pm_ops, pci1xxxx_spi_suspend,
		pci1xxxx_spi_resume);

		static struct pci_driver pci1xxxx_spi_driver = {
		.name = DRV_NAME,
		.id_table = pci1xxxx_spi_pci_id_table,
		.probe = pci1xxxx_spi_probe,
		.driver = {
		.pm = pm_sleep_ptr(&spi_pm_ops),
		},
		};

		module_pci_driver(pci1xxxx_spi_driver);