Commit 7b801dee authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Init DDI outputs based on port_mask on skl+ 



Instead of listing every platform's possible DDI outputs
in intel_setup_outputs() just loop over the new port_mask
to achieve the same thing.

HSW/BDW were left as is since they still look at the straps
as well.

DSI is still a mess. For now just check for the relevant
platforms explicitly.

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230616140820.11726-7-ville.syrjala@linux.intel.com
parent 39432640

drivers/gpu/drm/i915/display/intel_display.c

+13 −67
Original line number Diff line number Diff line
@@ -7408,73 +7408,19 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv) 
	if (!HAS_DISPLAY(dev_priv))

		return;



	if (IS_METEORLAKE(dev_priv)) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_TC1);

		intel_ddi_init(dev_priv, PORT_TC2);

		intel_ddi_init(dev_priv, PORT_TC3);

		intel_ddi_init(dev_priv, PORT_TC4);

	} else if (IS_DG2(dev_priv)) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_C);

		intel_ddi_init(dev_priv, PORT_D_XELPD);

		intel_ddi_init(dev_priv, PORT_TC1);

	} else if (IS_ALDERLAKE_P(dev_priv)) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_TC1);

		intel_ddi_init(dev_priv, PORT_TC2);

		intel_ddi_init(dev_priv, PORT_TC3);

		intel_ddi_init(dev_priv, PORT_TC4);

		icl_dsi_init(dev_priv);

	} else if (IS_ALDERLAKE_S(dev_priv)) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_TC1);

		intel_ddi_init(dev_priv, PORT_TC2);

		intel_ddi_init(dev_priv, PORT_TC3);

		intel_ddi_init(dev_priv, PORT_TC4);

	} else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_TC1);

		intel_ddi_init(dev_priv, PORT_TC2);

	} else if (DISPLAY_VER(dev_priv) >= 12) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_TC1);

		intel_ddi_init(dev_priv, PORT_TC2);

		intel_ddi_init(dev_priv, PORT_TC3);

		intel_ddi_init(dev_priv, PORT_TC4);

		intel_ddi_init(dev_priv, PORT_TC5);

		intel_ddi_init(dev_priv, PORT_TC6);

		icl_dsi_init(dev_priv);

	} else if (IS_JSL_EHL(dev_priv)) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_C);

		intel_ddi_init(dev_priv, PORT_D);

		icl_dsi_init(dev_priv);

	} else if (DISPLAY_VER(dev_priv) == 11) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_C);

		intel_ddi_init(dev_priv, PORT_D);

		intel_ddi_init(dev_priv, PORT_E);

		intel_ddi_init(dev_priv, PORT_F);

	if (DISPLAY_VER(dev_priv) >= 9) {

		enum port port;



		for_each_port_masked(port, DISPLAY_RUNTIME_INFO(dev_priv)->port_mask)

			intel_ddi_init(dev_priv, port);



		/* FIXME do something about DSI */

		if (IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv) ||

		    DISPLAY_VER(dev_priv) == 11)

			icl_dsi_init(dev_priv);

	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_C);



		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

			vlv_dsi_init(dev_priv);

	} else if (DISPLAY_VER(dev_priv) >= 9) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_C);

		intel_ddi_init(dev_priv, PORT_D);

		intel_ddi_init(dev_priv, PORT_E);

	} else if (HAS_DDI(dev_priv)) {

		u32 found;