Commit 7b6f8467 authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: Support sector layout on Tegra194 



Tegra194 has a special physical address bit that enables some memory
swizzling logic to support different sector layouts. Support the bit
that selects the sector layout which is passed in the framebuffer
modifier.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 05d1adfe

drivers/gpu/drm/tegra/dc.c

+7 −0
Original line number Original line Diff line number Diff line
@@ -2325,6 +2325,7 @@ static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 
	.supports_interlacing = false,

	.supports_interlacing = false,

	.supports_cursor = false,

	.supports_cursor = false,

	.supports_block_linear = false,

	.supports_block_linear = false,

	.supports_sector_layout = false,

	.has_legacy_blending = true,

	.has_legacy_blending = true,

	.pitch_align = 8,

	.pitch_align = 8,

	.has_powergate = false,

	.has_powergate = false,
@@ -2344,6 +2345,7 @@ static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 
	.supports_interlacing = false,

	.supports_interlacing = false,

	.supports_cursor = false,

	.supports_cursor = false,

	.supports_block_linear = false,

	.supports_block_linear = false,

	.supports_sector_layout = false,

	.has_legacy_blending = true,

	.has_legacy_blending = true,

	.pitch_align = 8,

	.pitch_align = 8,

	.has_powergate = false,

	.has_powergate = false,
@@ -2363,6 +2365,7 @@ static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 
	.supports_interlacing = false,

	.supports_interlacing = false,

	.supports_cursor = false,

	.supports_cursor = false,

	.supports_block_linear = false,

	.supports_block_linear = false,

	.supports_sector_layout = false,

	.has_legacy_blending = true,

	.has_legacy_blending = true,

	.pitch_align = 64,

	.pitch_align = 64,

	.has_powergate = true,

	.has_powergate = true,
@@ -2382,6 +2385,7 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 
	.supports_interlacing = true,

	.supports_interlacing = true,

	.supports_cursor = true,

	.supports_cursor = true,

	.supports_block_linear = true,

	.supports_block_linear = true,

	.supports_sector_layout = false,

	.has_legacy_blending = false,

	.has_legacy_blending = false,

	.pitch_align = 64,

	.pitch_align = 64,

	.has_powergate = true,

	.has_powergate = true,
@@ -2401,6 +2405,7 @@ static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 
	.supports_interlacing = true,

	.supports_interlacing = true,

	.supports_cursor = true,

	.supports_cursor = true,

	.supports_block_linear = true,

	.supports_block_linear = true,

	.supports_sector_layout = false,

	.has_legacy_blending = false,

	.has_legacy_blending = false,

	.pitch_align = 64,

	.pitch_align = 64,

	.has_powergate = true,

	.has_powergate = true,
@@ -2454,6 +2459,7 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 
	.supports_interlacing = true,

	.supports_interlacing = true,

	.supports_cursor = true,

	.supports_cursor = true,

	.supports_block_linear = true,

	.supports_block_linear = true,

	.supports_sector_layout = false,

	.has_legacy_blending = false,

	.has_legacy_blending = false,

	.pitch_align = 64,

	.pitch_align = 64,

	.has_powergate = false,

	.has_powergate = false,
@@ -2502,6 +2508,7 @@ static const struct tegra_dc_soc_info tegra194_dc_soc_info = { 
	.supports_interlacing = true,

	.supports_interlacing = true,

	.supports_cursor = true,

	.supports_cursor = true,

	.supports_block_linear = true,

	.supports_block_linear = true,

	.supports_sector_layout = true,

	.has_legacy_blending = false,

	.has_legacy_blending = false,

	.pitch_align = 64,

	.pitch_align = 64,

	.has_powergate = false,

	.has_powergate = false,

drivers/gpu/drm/tegra/dc.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -52,6 +52,7 @@ struct tegra_dc_soc_info { 
	bool supports_interlacing;

	bool supports_interlacing;

	bool supports_cursor;

	bool supports_cursor;

	bool supports_block_linear;

	bool supports_block_linear;

	bool supports_sector_layout;

	bool has_legacy_blending;

	bool has_legacy_blending;

	unsigned int pitch_align;

	unsigned int pitch_align;

	bool has_powergate;

	bool has_powergate;

drivers/gpu/drm/tegra/drm.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -24,6 +24,9 @@ 
#include "hub.h"

#include "hub.h"

#include "trace.h"

#include "trace.h"





/* XXX move to include/uapi/drm/drm_fourcc.h? */

#define DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT BIT(22)



struct reset_control;

struct reset_control;





#ifdef CONFIG_DRM_FBDEV_EMULATION

#ifdef CONFIG_DRM_FBDEV_EMULATION

drivers/gpu/drm/tegra/fb.c

+9 −0
Original line number Original line Diff line number Diff line
@@ -44,6 +44,15 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, 
{

{

	uint64_t modifier = framebuffer->modifier;

	uint64_t modifier = framebuffer->modifier;





	if ((modifier >> 56) == DRM_FORMAT_MOD_VENDOR_NVIDIA) {

		if ((modifier & DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) == 0)

			tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_TEGRA;

		else

			tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_GPU;



		modifier &= ~DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT;

	}



	switch (modifier) {

	switch (modifier) {

	case DRM_FORMAT_MOD_LINEAR:

	case DRM_FORMAT_MOD_LINEAR:

		tiling->mode = TEGRA_BO_TILING_MODE_PITCH;

		tiling->mode = TEGRA_BO_TILING_MODE_PITCH;

drivers/gpu/drm/tegra/gem.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -21,9 +21,15 @@ enum tegra_bo_tiling_mode { 
	TEGRA_BO_TILING_MODE_BLOCK,

	TEGRA_BO_TILING_MODE_BLOCK,

};

};





enum tegra_bo_sector_layout {

	TEGRA_BO_SECTOR_LAYOUT_TEGRA,

	TEGRA_BO_SECTOR_LAYOUT_GPU,

};



struct tegra_bo_tiling {

struct tegra_bo_tiling {

	enum tegra_bo_tiling_mode mode;

	enum tegra_bo_tiling_mode mode;

	unsigned long value;

	unsigned long value;

	enum tegra_bo_sector_layout sector_layout;

};

};





struct tegra_bo {

struct tegra_bo {