Commit 7b454b3a authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
Browse files

drm/amdgpu: Use different gart table parameters for 2-level gart table 



If use gart for FB translation, we will squeeze vram into
sysvm aperture. This requires 2 level gart table. Add
page table depth and page table block size parameters
to gmc. This is prepare work to 2-level gart table
construction

Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarChristian Konig <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f527f310

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

+3 −0
Original line number Diff line number Diff line
@@ -244,6 +244,9 @@ struct amdgpu_gmc { 
	struct amdgpu_xgmi xgmi;

	struct amdgpu_irq_src	ecc_irq;

	int noretry;



	uint32_t	vmid0_page_table_block_size;

	uint32_t	vmid0_page_table_depth;

};



#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+4 −1
Original line number Diff line number Diff line
@@ -189,7 +189,10 @@ static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 


	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

			adev->gmc.vmid0_page_table_depth);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

			adev->gmc.vmid0_page_table_block_size);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);

	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+9 −0
Original line number Diff line number Diff line
@@ -1363,6 +1363,15 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 
		WARN(1, "VEGA10 PCIE GART already initialized\n");

		return 0;

	}



	if (adev->gmc.xgmi.connected_to_cpu) {

		adev->gmc.vmid0_page_table_depth = 1;

		adev->gmc.vmid0_page_table_block_size = 12;

	} else {

		adev->gmc.vmid0_page_table_depth = 0;

		adev->gmc.vmid0_page_table_block_size = 0;

	}



	/* Initialize common gart structure */

	r = amdgpu_gart_init(adev);

	if (r)

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

+4 −1
Original line number Diff line number Diff line
@@ -198,7 +198,10 @@ static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev) 


	tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

			adev->gmc.vmid0_page_table_depth);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

			adev->gmc.vmid0_page_table_block_size);

	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);

	WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp);