Unverified Commit 7b3bee09 authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown
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ASoC: fsl_sai: Drop TMR/RMR settings for synchronous mode 



Tx synchronous with Rx: The RMR is the word mask register, it is used
to mask any word in the frame, it is not relating to clock generation,
So it is no need to be changed when Tx is going to be enabled.

Rx synchronous with Tx: The TMR is the word mask register, it is used
to mask any word in the frame, it is not relating to clock generation,
So it is no need to be changed when Rx is going to be enabled.

Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20200805063413.4610-3-shengjiu.wang@nxp.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 94741eba

sound/soc/fsl/fsl_sai.c

+1 −6
Original line number Diff line number Diff line
@@ -488,8 +488,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 
	/*

	 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will

	 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),

	 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync

	 * error.

	 * RCR5(TCR5) for playback(capture), or there will be sync error.

	 */



	if (!sai->is_slave_mode) {
@@ -500,8 +499,6 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 
			regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs),

				FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |

				FSL_SAI_CR5_FBT_MASK, val_cr5);

			regmap_write(sai->regmap, FSL_SAI_TMR,

				~0UL - ((1 << channels) - 1));

		} else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {

			regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs),

				FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
@@ -509,8 +506,6 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 
			regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs),

				FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |

				FSL_SAI_CR5_FBT_MASK, val_cr5);

			regmap_write(sai->regmap, FSL_SAI_RMR,

				~0UL - ((1 << channels) - 1));

		}

	}