Commit 7b0f95f2 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'timers-v6.3-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 

Pull clocksource/event changes from Daniel Lezcano:

   - Add rktimer for rv1126 Rockchip based board (Jagan Teki)

   - Initialize hrtimer based broadcast clock event device on RISC-V
     before C3STOP can be used (Conor Dooley)

   - Add DT binding for RISC-V timer and add the C3STOP flag if the DT
     tells the timer can not wake up the CPU (Anup Patel)

   - Increase the RISC-V timer rating as it is more efficient than mmio
     timers (Samuel Holland)

   - Drop obsolete dependency on COMPILE_TEST on microchip-pit64b as the
     OF is already depending on it (Jean Delvare)

   - Mark sh_cmt, sh_tmu, em_sti drivers as non-removable (Uwe
     Kleine-König)

   - Add binding description for mediatek,mt8365-systimer (Bernhard
     Rosenkränzer)

   - Add compatibles for T-Head's C9xx (Icenowy Zheng)

   - Restrict the microchip-pit64b compilation to the ARM architecture
     and add the delay timer (Claudiu Beznea)

   - Set the static key to select the SBI or Sstc timer sooner to prevent
     the first call to use the SBI while Sstc must be used (Matt Evans)

   - Add the CLOCK_EVT_FEAT_DYNIRQ flag to optimize the timer wake up on
     the sun4i platform (Yangtao Li)

Link: https://lore.kernel/org/r/b7d1d982-d717-2930-b353-19b92cbe390f@linaro.org
parents 5b268d8a 5ccb51b0

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ Required properties: 


	For those SoCs that use CPUX

	* "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX)

	* "mediatek,mt8365-systimer" for MT8365 compatible timers (CPUX)



- reg: Should contain location and length for timer register.

- clocks: Should contain system clock.

Documentation/devicetree/bindings/timer/riscv,timer.yaml

0 → 100644
+52 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: RISC-V timer



maintainers:

  - Anup Patel <anup@brainfault.org>



description: |+

  RISC-V platforms always have a RISC-V timer device for the supervisor-mode

  based on the time CSR defined by the RISC-V privileged specification. The

  timer interrupts of this device are configured using the RISC-V SBI Time

  extension or the RISC-V Sstc extension.



  The clock frequency of RISC-V timer device is specified via the

  "timebase-frequency" DT property of "/cpus" DT node which is described

  in Documentation/devicetree/bindings/riscv/cpus.yaml



properties:

  compatible:

    enum:

      - riscv,timer



  interrupts-extended:

    minItems: 1

    maxItems: 4096   # Should be enough?



  riscv,timer-cannot-wake-cpu:

    type: boolean

    description:

      If present, the timer interrupt cannot wake up the CPU from one or

      more suspend/idle states.



additionalProperties: false



required:

  - compatible

  - interrupts-extended



examples:

  - |

    timer {

      compatible = "riscv,timer";

      interrupts-extended = <&cpu1intc 5>,

                            <&cpu2intc 5>,

                            <&cpu3intc 5>,

                            <&cpu4intc 5>;

    };

...

Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ properties: 
      - items:

          - enum:

              - rockchip,rv1108-timer

              - rockchip,rv1126-timer

              - rockchip,rk3036-timer

              - rockchip,rk3128-timer

              - rockchip,rk3188-timer

Documentation/devicetree/bindings/timer/sifive,clint.yaml

+8 −0
Original line number Diff line number Diff line
@@ -20,6 +20,10 @@ description: 
  property of "/cpus" DT node. The "timebase-frequency" DT property is

  described in Documentation/devicetree/bindings/riscv/cpus.yaml



  T-Head C906/C910 CPU cores include an implementation of CLINT too, however

  their implementation lacks a memory-mapped MTIME register, thus not

  compatible with SiFive ones.



properties:

  compatible:

    oneOf:
@@ -29,6 +33,10 @@ properties: 
              - starfive,jh7100-clint

              - canaan,k210-clint

          - const: sifive,clint0

      - items:

          - enum:

              - allwinner,sun20i-d1-clint

          - const: thead,c900-clint

      - items:

          - const: sifive,clint0

          - const: riscv,clint0

arch/riscv/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ config 32BIT 


config RISCV

	def_bool y

	select ARCH_CLOCKSOURCE_INIT

	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION

	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2

	select ARCH_HAS_BINFMT_FLAT