Commit 7abb3e4e authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/mm' into for-next/core 

* for-next/mm:
  arm64: fix build warning for ARM64_MEMSTART_SHIFT
  arm64: Remove unsued extern declaration init_mem_pgprot()
  arm64/mm: Set only the PTE_DIRTY bit while preserving the HW dirty state
  arm64/mm: Add pte_rdonly() helper
  arm64/mm: Directly use ID_AA64MMFR2_EL1_VARange_MASK
  arm64/mm: Replace an open coding with ID_AA64MMFR1_EL1_HAFDBS_MASK
parents 438ddc3c 4e0bacd6

arch/arm64/include/asm/kernel-pgtable.h

+0 −27
Original line number Diff line number Diff line
@@ -118,31 +118,4 @@ 
#define SWAPPER_RX_MMUFLAGS	(SWAPPER_RW_MMUFLAGS | PTE_RDONLY)

#endif



/*

 * To make optimal use of block mappings when laying out the linear

 * mapping, round down the base of physical memory to a size that can

 * be mapped efficiently, i.e., either PUD_SIZE (4k granule) or PMD_SIZE

 * (64k granule), or a multiple that can be mapped using contiguous bits

 * in the page tables: 32 * PMD_SIZE (16k granule)

 */

#if defined(CONFIG_ARM64_4K_PAGES)

#define ARM64_MEMSTART_SHIFT		PUD_SHIFT

#elif defined(CONFIG_ARM64_16K_PAGES)

#define ARM64_MEMSTART_SHIFT		CONT_PMD_SHIFT

#else

#define ARM64_MEMSTART_SHIFT		PMD_SHIFT

#endif



/*

 * sparsemem vmemmap imposes an additional requirement on the alignment of

 * memstart_addr, due to the fact that the base of the vmemmap region

 * has a direct correspondence, and needs to appear sufficiently aligned

 * in the virtual address space.

 */

#if ARM64_MEMSTART_SHIFT < SECTION_SIZE_BITS

#define ARM64_MEMSTART_ALIGN	(1UL << SECTION_SIZE_BITS)

#else

#define ARM64_MEMSTART_ALIGN	(1UL << ARM64_MEMSTART_SHIFT)

#endif



#endif	/* __ASM_KERNEL_PGTABLE_H */

arch/arm64/include/asm/mmu.h

+0 −1
Original line number Diff line number Diff line
@@ -64,7 +64,6 @@ extern void arm64_memblock_init(void); 
extern void paging_init(void);

extern void bootmem_init(void);

extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);

extern void init_mem_pgprot(void);

extern void create_mapping_noalloc(phys_addr_t phys, unsigned long virt,

				   phys_addr_t size, pgprot_t prot);

extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,

arch/arm64/include/asm/pgtable.h

+5 −3
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 
#define pte_young(pte)		(!!(pte_val(pte) & PTE_AF))

#define pte_special(pte)	(!!(pte_val(pte) & PTE_SPECIAL))

#define pte_write(pte)		(!!(pte_val(pte) & PTE_WRITE))

#define pte_rdonly(pte)		(!!(pte_val(pte) & PTE_RDONLY))

#define pte_user(pte)		(!!(pte_val(pte) & PTE_USER))

#define pte_user_exec(pte)	(!(pte_val(pte) & PTE_UXN))

#define pte_cont(pte)		(!!(pte_val(pte) & PTE_CONT))
@@ -120,7 +121,7 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 
	(__boundary - 1 < (end) - 1) ? __boundary : (end);			\

})



#define pte_hw_dirty(pte)	(pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))

#define pte_hw_dirty(pte)	(pte_write(pte) && !pte_rdonly(pte))

#define pte_sw_dirty(pte)	(!!(pte_val(pte) & PTE_DIRTY))

#define pte_dirty(pte)		(pte_sw_dirty(pte) || pte_hw_dirty(pte))
@@ -212,7 +213,7 @@ static inline pte_t pte_wrprotect(pte_t pte) 
	 * clear), set the PTE_DIRTY bit.

	 */

	if (pte_hw_dirty(pte))

		pte = pte_mkdirty(pte);

		pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));



	pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));

	pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
@@ -823,7 +824,8 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 
			      PTE_ATTRINDX_MASK;

	/* preserve the hardware dirty information */

	if (pte_hw_dirty(pte))

		pte = pte_mkdirty(pte);

		pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));



	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);

	return pte;

}

arch/arm64/kernel/head.S

+2 −2
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ SYM_CODE_START(primary_entry) 
	 */

#if VA_BITS > 48

	mrs_s	x0, SYS_ID_AA64MMFR2_EL1

	tst	x0, #0xf << ID_AA64MMFR2_EL1_VARange_SHIFT

	tst	x0, ID_AA64MMFR2_EL1_VARange_MASK

	mov	x0, #VA_BITS

	mov	x25, #VA_BITS_MIN

	csel	x25, x25, x0, eq
@@ -756,7 +756,7 @@ SYM_FUNC_START(__cpu_secondary_check52bitva) 
	b.ne	2f



	mrs_s	x0, SYS_ID_AA64MMFR2_EL1

	and	x0, x0, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT)

	and	x0, x0, ID_AA64MMFR2_EL1_VARange_MASK

	cbnz	x0, 2f



	update_early_cpu_boot_status \

arch/arm64/mm/init.c

+27 −0
Original line number Diff line number Diff line
@@ -73,6 +73,33 @@ phys_addr_t __ro_after_init arm64_dma_phys_limit; 


#define DEFAULT_CRASH_KERNEL_LOW_SIZE	(128UL << 20)



/*

 * To make optimal use of block mappings when laying out the linear

 * mapping, round down the base of physical memory to a size that can

 * be mapped efficiently, i.e., either PUD_SIZE (4k granule) or PMD_SIZE

 * (64k granule), or a multiple that can be mapped using contiguous bits

 * in the page tables: 32 * PMD_SIZE (16k granule)

 */

#if defined(CONFIG_ARM64_4K_PAGES)

#define ARM64_MEMSTART_SHIFT		PUD_SHIFT

#elif defined(CONFIG_ARM64_16K_PAGES)

#define ARM64_MEMSTART_SHIFT		CONT_PMD_SHIFT

#else

#define ARM64_MEMSTART_SHIFT		PMD_SHIFT

#endif



/*

 * sparsemem vmemmap imposes an additional requirement on the alignment of

 * memstart_addr, due to the fact that the base of the vmemmap region

 * has a direct correspondence, and needs to appear sufficiently aligned

 * in the virtual address space.

 */

#if ARM64_MEMSTART_SHIFT < SECTION_SIZE_BITS

#define ARM64_MEMSTART_ALIGN	(1UL << SECTION_SIZE_BITS)

#else

#define ARM64_MEMSTART_ALIGN	(1UL << ARM64_MEMSTART_SHIFT)

#endif



static int __init reserve_crashkernel_low(unsigned long long low_size)

{

	unsigned long long low_base;