Commit 7aa6f1a1 authored by Marijn Suijten's avatar Marijn Suijten Committed by Dmitry Baryshkov
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drm/msm/dpu: Implement DSC binding to PP block for CTL V1 



All V1 CTL blocks (active CTLs) explicitly bind the pixel output from a
DSC block to a PINGPONG block by setting the PINGPONG index in a DSC
hardware register.

Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/515698/
Link: https://lore.kernel.org/r/20221221231943.1961117-8-marijn.suijten@somainline.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 4ba5a4ad

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+3 −0
Original line number Diff line number Diff line
@@ -1829,6 +1829,9 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc, 
	if (hw_pp->ops.setup_dsc)

		hw_pp->ops.setup_dsc(hw_pp);



	if (hw_dsc->ops.dsc_bind_pingpong_blk)

		hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, true, hw_pp->idx);



	if (hw_pp->ops.enable_dsc)

		hw_pp->ops.enable_dsc(hw_pp);

}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+9 −0
Original line number Diff line number Diff line
@@ -273,6 +273,15 @@ enum { 
	DPU_VBIF_MAX

};



/**

 * DSC features

 * @DPU_DSC_OUTPUT_CTRL       Configure which PINGPONG block gets

 *                            the pixel output from this DSC.

 */

enum {

	DPU_DSC_OUTPUT_CTRL = 0x1,

};



/**

 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU

 * @name:              string name for debug purposes

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

+27 −0
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
#define DSC_RANGE_MAX_QP                0x0B0

#define DSC_RANGE_BPG_OFFSET            0x0EC



#define DSC_CTL(m) (0x1800 - 0x3FC * (m - DSC_0))



static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)

{

	struct dpu_hw_blk_reg_map *c = &dsc->hw;
@@ -150,6 +152,29 @@ static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc, 
	}

}



static void dpu_hw_dsc_bind_pingpong_blk(

		struct dpu_hw_dsc *hw_dsc,

		bool enable,

		const enum dpu_pingpong pp)

{

	struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;

	int mux_cfg = 0xF;

	u32 dsc_ctl_offset;



	dsc_ctl_offset = DSC_CTL(hw_dsc->idx);



	if (enable)

		mux_cfg = (pp - PINGPONG_0) & 0x7;



	DRM_DEBUG_KMS("%s dsc:%d %s pp:%d\n",

			enable ? "Binding" : "Unbinding",

			hw_dsc->idx - DSC_0,

			enable ? "to" : "from",

			pp - PINGPONG_0);



	DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg);

}



static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,

				       const struct dpu_mdss_cfg *m,

				       void __iomem *addr,
@@ -174,6 +199,8 @@ static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops, 
	ops->dsc_disable = dpu_hw_dsc_disable;

	ops->dsc_config = dpu_hw_dsc_config;

	ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;

	if (cap & BIT(DPU_DSC_OUTPUT_CTRL))

		ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;

};



struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

+4 −0
Original line number Diff line number Diff line
@@ -42,6 +42,10 @@ struct dpu_hw_dsc_ops { 
	 */

	void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,

				  struct drm_dsc_config *dsc);



	void (*dsc_bind_pingpong_blk)(struct dpu_hw_dsc *hw_dsc,

				  bool enable,

				  enum dpu_pingpong pp);

};



struct dpu_hw_dsc {