Loading drivers/gpu/drm/nouveau/nouveau_dma.h +0 −5 Original line number Original line Diff line number Diff line Loading @@ -45,11 +45,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); */ */ #define NOUVEAU_DMA_SKIPS (128 / 4) #define NOUVEAU_DMA_SKIPS (128 / 4) /* Hardcoded object assignments to subchannels (subchannel id). */ enum { NvSubSw = 1, }; /* Object handles - for stuff that's doesn't use handle == oclass. */ /* Object handles - for stuff that's doesn't use handle == oclass. */ enum { enum { NvDmaFB = 0x80000002, NvDmaFB = 0x80000002, Loading drivers/gpu/drm/nouveau/nv04_fence.c +5 −6 Original line number Original line Diff line number Diff line Loading @@ -21,12 +21,12 @@ * * * Authors: Ben Skeggs * Authors: Ben Skeggs */ */ #include "nouveau_drv.h" #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_dma.h" #include "nouveau_fence.h" #include "nouveau_fence.h" #include <nvif/if0004.h> #include <nvif/if0004.h> #include <nvif/push006c.h> struct nv04_fence_chan { struct nv04_fence_chan { struct nouveau_fence_chan base; struct nouveau_fence_chan base; Loading @@ -39,12 +39,11 @@ struct nv04_fence_priv { static int static int nv04_fence_emit(struct nouveau_fence *fence) nv04_fence_emit(struct nouveau_fence *fence) { { struct nouveau_channel *chan = fence->channel; struct nvif_push *push = fence->channel->chan.push; int ret = RING_SPACE(chan, 2); int ret = PUSH_WAIT(push, 2); if (ret == 0) { if (ret == 0) { BEGIN_NV04(chan, NvSubSw, 0x0150, 1); PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno); OUT_RING (chan, fence->base.seqno); PUSH_KICK(push); FIRE_RING (chan); } } return ret; return ret; } } Loading drivers/gpu/drm/nouveau/nv10_fence.c +6 −6 Original line number Original line Diff line number Diff line Loading @@ -21,20 +21,20 @@ * * * Authors: Ben Skeggs <bskeggs@redhat.com> * Authors: Ben Skeggs <bskeggs@redhat.com> */ */ #include "nouveau_drv.h" #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_dma.h" #include "nv10_fence.h" #include "nv10_fence.h" #include <nvif/push006c.h> int int nv10_fence_emit(struct nouveau_fence *fence) nv10_fence_emit(struct nouveau_fence *fence) { { struct nouveau_channel *chan = fence->channel; struct nvif_push *push = fence->channel->chan.push; int ret = RING_SPACE(chan, 2); int ret = PUSH_WAIT(push, 2); if (ret == 0) { if (ret == 0) { BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1); PUSH_NVSQ(push, NV06E, NV10_SUBCHAN_REF_CNT, fence->base.seqno); OUT_RING (chan, fence->base.seqno); PUSH_KICK(push); FIRE_RING (chan); } } return ret; return ret; } } Loading drivers/gpu/drm/nouveau/nv84_fence.c +13 −11 Original line number Original line Diff line number Diff line Loading @@ -21,7 +21,6 @@ * * * Authors: Ben Skeggs * Authors: Ben Skeggs */ */ #include "nouveau_drv.h" #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_dma.h" #include "nouveau_fence.h" #include "nouveau_fence.h" Loading @@ -29,20 +28,23 @@ #include "nv50_display.h" #include "nv50_display.h" #include <nvif/push206e.h> static int static int nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { { int ret = RING_SPACE(chan, 8); struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 8); if (ret == 0) { if (ret == 0) { BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle); OUT_RING (chan, chan->vram.handle); PUSH_NVSQ(push, NV826F, BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), OUT_RING (chan, upper_32_bits(virtual)); NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), OUT_RING (chan, lower_32_bits(virtual)); NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, OUT_RING (chan, sequence); NV84_SUBCHAN_SEMAPHORE_TRIGGER, OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, OUT_RING (chan, 0x00000000); NV84_SUBCHAN_UEVENT, 0x00000000); FIRE_RING (chan); PUSH_KICK(push); } } return ret; return ret; } } Loading drivers/gpu/drm/nouveau/nvc0_fence.c +12 −9 Original line number Original line Diff line number Diff line Loading @@ -21,25 +21,28 @@ * * * Authors: Ben Skeggs * Authors: Ben Skeggs */ */ #include "nouveau_drv.h" #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_dma.h" #include "nouveau_fence.h" #include "nouveau_fence.h" #include "nv50_display.h" #include "nv50_display.h" #include <nvif/push906f.h> static int static int nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { { int ret = RING_SPACE(chan, 6); struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 6); if (ret == 0) { if (ret == 0) { BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); PUSH_NVSQ(push, NV906F, OUT_RING (chan, upper_32_bits(virtual)); NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), OUT_RING (chan, lower_32_bits(virtual)); NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), OUT_RING (chan, sequence); NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); NV84_SUBCHAN_SEMAPHORE_TRIGGER, OUT_RING (chan, 0x00000000); NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, FIRE_RING (chan); NV84_SUBCHAN_UEVENT, 0x00000000); PUSH_KICK(push); } } return ret; return ret; } } Loading Loading
drivers/gpu/drm/nouveau/nouveau_dma.h +0 −5 Original line number Original line Diff line number Diff line Loading @@ -45,11 +45,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); */ */ #define NOUVEAU_DMA_SKIPS (128 / 4) #define NOUVEAU_DMA_SKIPS (128 / 4) /* Hardcoded object assignments to subchannels (subchannel id). */ enum { NvSubSw = 1, }; /* Object handles - for stuff that's doesn't use handle == oclass. */ /* Object handles - for stuff that's doesn't use handle == oclass. */ enum { enum { NvDmaFB = 0x80000002, NvDmaFB = 0x80000002, Loading
drivers/gpu/drm/nouveau/nv04_fence.c +5 −6 Original line number Original line Diff line number Diff line Loading @@ -21,12 +21,12 @@ * * * Authors: Ben Skeggs * Authors: Ben Skeggs */ */ #include "nouveau_drv.h" #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_dma.h" #include "nouveau_fence.h" #include "nouveau_fence.h" #include <nvif/if0004.h> #include <nvif/if0004.h> #include <nvif/push006c.h> struct nv04_fence_chan { struct nv04_fence_chan { struct nouveau_fence_chan base; struct nouveau_fence_chan base; Loading @@ -39,12 +39,11 @@ struct nv04_fence_priv { static int static int nv04_fence_emit(struct nouveau_fence *fence) nv04_fence_emit(struct nouveau_fence *fence) { { struct nouveau_channel *chan = fence->channel; struct nvif_push *push = fence->channel->chan.push; int ret = RING_SPACE(chan, 2); int ret = PUSH_WAIT(push, 2); if (ret == 0) { if (ret == 0) { BEGIN_NV04(chan, NvSubSw, 0x0150, 1); PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno); OUT_RING (chan, fence->base.seqno); PUSH_KICK(push); FIRE_RING (chan); } } return ret; return ret; } } Loading
drivers/gpu/drm/nouveau/nv10_fence.c +6 −6 Original line number Original line Diff line number Diff line Loading @@ -21,20 +21,20 @@ * * * Authors: Ben Skeggs <bskeggs@redhat.com> * Authors: Ben Skeggs <bskeggs@redhat.com> */ */ #include "nouveau_drv.h" #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_dma.h" #include "nv10_fence.h" #include "nv10_fence.h" #include <nvif/push006c.h> int int nv10_fence_emit(struct nouveau_fence *fence) nv10_fence_emit(struct nouveau_fence *fence) { { struct nouveau_channel *chan = fence->channel; struct nvif_push *push = fence->channel->chan.push; int ret = RING_SPACE(chan, 2); int ret = PUSH_WAIT(push, 2); if (ret == 0) { if (ret == 0) { BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1); PUSH_NVSQ(push, NV06E, NV10_SUBCHAN_REF_CNT, fence->base.seqno); OUT_RING (chan, fence->base.seqno); PUSH_KICK(push); FIRE_RING (chan); } } return ret; return ret; } } Loading
drivers/gpu/drm/nouveau/nv84_fence.c +13 −11 Original line number Original line Diff line number Diff line Loading @@ -21,7 +21,6 @@ * * * Authors: Ben Skeggs * Authors: Ben Skeggs */ */ #include "nouveau_drv.h" #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_dma.h" #include "nouveau_fence.h" #include "nouveau_fence.h" Loading @@ -29,20 +28,23 @@ #include "nv50_display.h" #include "nv50_display.h" #include <nvif/push206e.h> static int static int nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { { int ret = RING_SPACE(chan, 8); struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 8); if (ret == 0) { if (ret == 0) { BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle); OUT_RING (chan, chan->vram.handle); PUSH_NVSQ(push, NV826F, BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), OUT_RING (chan, upper_32_bits(virtual)); NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), OUT_RING (chan, lower_32_bits(virtual)); NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, OUT_RING (chan, sequence); NV84_SUBCHAN_SEMAPHORE_TRIGGER, OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, OUT_RING (chan, 0x00000000); NV84_SUBCHAN_UEVENT, 0x00000000); FIRE_RING (chan); PUSH_KICK(push); } } return ret; return ret; } } Loading
drivers/gpu/drm/nouveau/nvc0_fence.c +12 −9 Original line number Original line Diff line number Diff line Loading @@ -21,25 +21,28 @@ * * * Authors: Ben Skeggs * Authors: Ben Skeggs */ */ #include "nouveau_drv.h" #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_dma.h" #include "nouveau_fence.h" #include "nouveau_fence.h" #include "nv50_display.h" #include "nv50_display.h" #include <nvif/push906f.h> static int static int nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { { int ret = RING_SPACE(chan, 6); struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 6); if (ret == 0) { if (ret == 0) { BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); PUSH_NVSQ(push, NV906F, OUT_RING (chan, upper_32_bits(virtual)); NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), OUT_RING (chan, lower_32_bits(virtual)); NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), OUT_RING (chan, sequence); NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); NV84_SUBCHAN_SEMAPHORE_TRIGGER, OUT_RING (chan, 0x00000000); NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, FIRE_RING (chan); NV84_SUBCHAN_UEVENT, 0x00000000); PUSH_KICK(push); } } return ret; return ret; } } Loading