Unverified Commit 7aa1cc10 authored by Charles Keepax's avatar Charles Keepax Committed by Mark Brown
Browse files

firmware: cs_dsp: Clear core reset for cache 



If the Halo registers are kept in the register cache the
HALO_CORE_RESET bit will be retained as 1 after reset is triggered in
cs_dsp_halo_start_core. This will cause subsequent writes to reset
the core which is not desired. Apart from this bit the rest of the
register bits are cacheable, so for safety sake clear the bit to
ensure the cache is consistent.

Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220105113026.18955-6-ckeepax@opensource.cirrus.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 5f2f5399

drivers/firmware/cirrus/cs_dsp.c

+10 −4
Original line number Diff line number Diff line
@@ -2744,10 +2744,16 @@ EXPORT_SYMBOL_GPL(cs_dsp_stop); 


static int cs_dsp_halo_start_core(struct cs_dsp *dsp)

{

	return regmap_update_bits(dsp->regmap,

				  dsp->base + HALO_CCM_CORE_CONTROL,

	int ret;



	ret = regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,

				 HALO_CORE_RESET | HALO_CORE_EN,

				 HALO_CORE_RESET | HALO_CORE_EN);

	if (ret)

		return ret;



	return regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,

				  HALO_CORE_RESET, 0);

}



static void cs_dsp_halo_stop_core(struct cs_dsp *dsp)