Commit 7a8a3430 authored by Timothy Pearson's avatar Timothy Pearson Committed by Alex Deucher
Browse files

amdgpu: Wrap FPU dependent functions in dc20 



dc20 containes several FPU-dependent functions without proper FPU
kernel mode enable/disable wrappers.  Add the required wrappers
for both x86 and POWER.

This enables Navi DC20 support for POWER systems.

v2: fix compilation

Signed-off-by: default avatarTimothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 16a9dea1

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+16 −4
Original line number Diff line number Diff line
@@ -2887,12 +2887,19 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
	bool voltage_supported = false;

	bool full_pstate_supported = false;

	bool dummy_pstate_supported = false;

	double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;

	context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = dc->debug.disable_dram_clock_change_vactive_support;

	double p_state_latency_us;



	if (fast_validate)

		return dcn20_validate_bandwidth_internal(dc, context, true);

	DC_FP_START();

	p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;

	context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =

		dc->debug.disable_dram_clock_change_vactive_support;



	if (fast_validate) {

		voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);



		DC_FP_END();

		return voltage_supported;

	}



	// Best case, we support full UCLK switch latency

	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
@@ -2921,6 +2928,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 
restore_dml_state:

	context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;



	DC_FP_END();

	return voltage_supported;

}
@@ -3442,6 +3450,8 @@ static bool dcn20_resource_construct( 
	enum dml_project dml_project_version =

			get_dml_project_version(ctx->asic_id.hw_internal_rev);



	DC_FP_START();



	ctx->dc_bios->regs = &bios_regs;

	pool->base.funcs = &dcn20_res_pool_funcs;
@@ -3739,10 +3749,12 @@ static bool dcn20_resource_construct( 
		pool->base.oem_device = NULL;

	}



	DC_FP_END();

	return true;



create_fail:



	DC_FP_END();

	dcn20_resource_destruct(pool);



	return false;