Commit 7a843c1d authored by Lang Cheng's avatar Lang Cheng Committed by Zheng Zengkai
Browse files

RDMA/hns: Remove unsupport cmdq mode 

mainline inclusion
from mainline-0110a1ed
commit v5.15-rc1
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I4QOTS
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git/commit/?id=0110a1ed0e8084f928170e055c87f4f046206908

---------------------------------------------------------------------

CMDQ support un-interrupt mode only, and firmware ignores this mode flag,
so remove it.

Fixes: a04ff739 ("RDMA/hns: Add command queue support for hip08 RoCE driver")
Link: https://lore.kernel.org/r/1629539607-33217-2-git-send-email-liangwenpeng@huawei.com


Signed-off-by: default avatarLang Cheng <chenglang@huawei.com>
Signed-off-by: default avatarWenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
sigend-off-by: default avatarGuofeng Yue <yueguofeng@hisilicon.com>

Reviewed-by: default avatarYangyang Li <liyangyang20@huawei.com>
Acked-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent b3f946fd

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+7 −14
Original line number Diff line number Diff line
@@ -1258,8 +1258,7 @@ static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 
{

	memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));

	desc->opcode = cpu_to_le16(opcode);

	desc->flag =

		cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);

	desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);

	if (is_read)

		desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);

	else
@@ -1298,16 +1297,11 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 
	/* Write to hardware */

	roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head);



	/* If the command is sync, wait for the firmware to write back,

	 * if multi descriptors to be sent, use the first one to check

	 */

	if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {

	do {

		if (hns_roce_cmq_csq_done(hr_dev))

			break;

		udelay(1);

	} while (++timeout < priv->cmq.tx_timeout);

	}



	if (hns_roce_cmq_csq_done(hr_dev)) {

		for (ret = 0, i = 0; i < num; i++) {
@@ -1771,8 +1765,7 @@ static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 
	if (ret)

		return ret;



	desc.flag =

		cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);

	desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN);

	desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);

	roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1);

	roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0);

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+7 −13
Original line number Diff line number Diff line
@@ -129,19 +129,13 @@ 


#define HNS_ROCE_V2_TABLE_CHUNK_SIZE		(1 << 18)



#define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT	0

#define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT	1

#define HNS_ROCE_CMD_FLAG_NEXT_SHIFT		2

#define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT	3

#define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT		4

#define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT	5



#define HNS_ROCE_CMD_FLAG_IN		BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)

#define HNS_ROCE_CMD_FLAG_OUT		BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)

#define HNS_ROCE_CMD_FLAG_NEXT		BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)

#define HNS_ROCE_CMD_FLAG_WR		BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)

#define HNS_ROCE_CMD_FLAG_NO_INTR	BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)

#define HNS_ROCE_CMD_FLAG_ERR_INTR	BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)

enum {

	HNS_ROCE_CMD_FLAG_IN = BIT(0),

	HNS_ROCE_CMD_FLAG_OUT = BIT(1),

	HNS_ROCE_CMD_FLAG_NEXT = BIT(2),

	HNS_ROCE_CMD_FLAG_WR = BIT(3),

	HNS_ROCE_CMD_FLAG_ERR_INTR = BIT(5),

};



#define HNS_ROCE_CMQ_DESC_NUM_S		3