Commit 7a5ad9b4 authored by Swapnil Jakhade's avatar Swapnil Jakhade Committed by Vinod Koul
Browse files

phy: cadence: Sierra: Update single link PCIe register configuration 



Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.

Signed-off-by: default avatarSwapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: default avatarAswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-11-sjakhade@cadence.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 36ce4163

drivers/phy/cadence/phy-cadence-sierra.c

+213 −1
Original line number Diff line number Diff line
@@ -36,7 +36,12 @@ 
#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG		0x4B

#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG		0x4F

#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG		0x50

#define SIERRA_CMN_PLLLC_DSMCORR_PREG			0x51

#define SIERRA_CMN_PLLLC_SS_PREG			0x52

#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG		0x53

#define SIERRA_CMN_PLLLC_SSTWOPT_PREG			0x54

#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG	0x62

#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG		0x63

#define SIERRA_CMN_REFRCV_PREG				0x98

#define SIERRA_CMN_REFRCV1_PREG				0xB8

#define SIERRA_CMN_PLLLC1_GEN_PREG			0xC2
@@ -52,6 +57,7 @@ 
#define SIERRA_DET_STANDEC_E_PREG			0x004

#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG		0x008

#define SIERRA_PSM_A0IN_TMR_PREG			0x009

#define SIERRA_PSM_A3IN_TMR_PREG			0x00C

#define SIERRA_PSM_DIAG_PREG				0x015

#define SIERRA_PSC_TX_A0_PREG				0x028

#define SIERRA_PSC_TX_A1_PREG				0x029
@@ -68,12 +74,15 @@ 
#define SIERRA_CLKPATH_BIASTRIM_PREG			0x04B

#define SIERRA_DFE_BIASTRIM_PREG			0x04C

#define SIERRA_DRVCTRL_ATTEN_PREG			0x06A

#define SIERRA_DRVCTRL_BOOST_PREG			0x06F

#define SIERRA_CLKPATHCTRL_TMR_PREG			0x081

#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG		0x085

#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG		0x086

#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG		0x087

#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG		0x088

#define SIERRA_CREQ_DCBIASATTEN_OVR_PREG		0x08C

#define SIERRA_CREQ_CCLKDET_MODE01_PREG			0x08E

#define SIERRA_RX_CTLE_CAL_PREG				0x08F

#define SIERRA_RX_CTLE_MAINTENANCE_PREG			0x091

#define SIERRA_CREQ_FSMCLK_SEL_PREG			0x092

#define SIERRA_CREQ_EQ_CTRL_PREG			0x093
@@ -123,15 +132,27 @@ 
#define SIERRA_DEQ_ALUT12				0x114

#define SIERRA_DEQ_ALUT13				0x115

#define SIERRA_DEQ_DFETAP_CTRL_PREG			0x128

#define SIERRA_DEQ_DFETAP0				0x129

#define SIERRA_DEQ_DFETAP1				0x12B

#define SIERRA_DEQ_DFETAP2				0x12D

#define SIERRA_DEQ_DFETAP3				0x12F

#define SIERRA_DEQ_DFETAP4				0x131

#define SIERRA_DFE_EN_1010_IGNORE_PREG			0x134

#define SIERRA_DEQ_PRECUR_PREG				0x138

#define SIERRA_DEQ_POSTCUR_PREG				0x140

#define SIERRA_DEQ_POSTCUR_DECR_PREG			0x142

#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150

#define SIERRA_DEQ_TAU_CTRL2_PREG			0x151

#define SIERRA_DEQ_TAU_CTRL3_PREG			0x152

#define SIERRA_DEQ_OPENEYE_CTRL_PREG			0x158

#define SIERRA_DEQ_PICTRL_PREG				0x161

#define SIERRA_CPICAL_TMRVAL_MODE1_PREG			0x170

#define SIERRA_CPICAL_TMRVAL_MODE0_PREG			0x171

#define SIERRA_CPICAL_PICNT_MODE1_PREG			0x174

#define SIERRA_CPI_OUTBUF_RATESEL_PREG			0x17C

#define SIERRA_CPI_TRIM_PREG				0x17F

#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG		0x183

#define SIERRA_EPI_CTRL_PREG				0x187

#define SIERRA_LFPSDET_SUPPORT_PREG			0x188

#define SIERRA_LFPSFILT_NS_PREG				0x18A

#define SIERRA_LFPSFILT_RD_PREG				0x18B
@@ -1162,6 +1183,146 @@ static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = { 
	.num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),

};



/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */

static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {

	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},

	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},

	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},

	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}

};



/* refclk100MHz_32b_PCIe_ln_no_ssc */

static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = {

	{0xFC08, SIERRA_DET_STANDEC_A_PREG},

	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},

	{0x1555, SIERRA_DFE_BIASTRIM_PREG},

	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},

	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},

	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},

	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},

	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},

	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},

	{0x9800, SIERRA_RX_CTLE_CAL_PREG},

	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},

	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},

	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},

	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},

	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},

	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},

	{0x0041, SIERRA_DEQ_GLUT0},

	{0x0082, SIERRA_DEQ_GLUT1},

	{0x00C3, SIERRA_DEQ_GLUT2},

	{0x0145, SIERRA_DEQ_GLUT3},

	{0x0186, SIERRA_DEQ_GLUT4},

	{0x09E7, SIERRA_DEQ_ALUT0},

	{0x09A6, SIERRA_DEQ_ALUT1},

	{0x0965, SIERRA_DEQ_ALUT2},

	{0x08E3, SIERRA_DEQ_ALUT3},

	{0x00FA, SIERRA_DEQ_DFETAP0},

	{0x00FA, SIERRA_DEQ_DFETAP1},

	{0x00FA, SIERRA_DEQ_DFETAP2},

	{0x00FA, SIERRA_DEQ_DFETAP3},

	{0x00FA, SIERRA_DEQ_DFETAP4},

	{0x000F, SIERRA_DEQ_PRECUR_PREG},

	{0x0280, SIERRA_DEQ_POSTCUR_PREG},

	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},

	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},

	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},

	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},

	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}

};



static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = {

	.reg_pairs = cdns_pcie_cmn_regs_no_ssc,

	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc),

};



static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = {

	.reg_pairs = cdns_pcie_ln_regs_no_ssc,

	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc),

};



/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */

static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = {

	{0x000E, SIERRA_CMN_PLLLC_MODE_PREG},

	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},

	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},

	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},

	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},

	{0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},

	{0x7F80, SIERRA_CMN_PLLLC_SS_PREG},

	{0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},

	{0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},

	{0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},

	{0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}

};



/* refclk100MHz_32b_PCIe_ln_int_ssc */

static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = {

	{0xFC08, SIERRA_DET_STANDEC_A_PREG},

	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},

	{0x1555, SIERRA_DFE_BIASTRIM_PREG},

	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},

	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},

	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},

	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},

	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},

	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},

	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},

	{0x9800, SIERRA_RX_CTLE_CAL_PREG},

	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},

	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},

	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},

	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},

	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},

	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},

	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},

	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},

	{0x0041, SIERRA_DEQ_GLUT0},

	{0x0082, SIERRA_DEQ_GLUT1},

	{0x00C3, SIERRA_DEQ_GLUT2},

	{0x0145, SIERRA_DEQ_GLUT3},

	{0x0186, SIERRA_DEQ_GLUT4},

	{0x09E7, SIERRA_DEQ_ALUT0},

	{0x09A6, SIERRA_DEQ_ALUT1},

	{0x0965, SIERRA_DEQ_ALUT2},

	{0x08E3, SIERRA_DEQ_ALUT3},

	{0x00FA, SIERRA_DEQ_DFETAP0},

	{0x00FA, SIERRA_DEQ_DFETAP1},

	{0x00FA, SIERRA_DEQ_DFETAP2},

	{0x00FA, SIERRA_DEQ_DFETAP3},

	{0x00FA, SIERRA_DEQ_DFETAP4},

	{0x000F, SIERRA_DEQ_PRECUR_PREG},

	{0x0280, SIERRA_DEQ_POSTCUR_PREG},

	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},

	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},

	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},

	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},

	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}

};



static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = {

	.reg_pairs = cdns_pcie_cmn_regs_int_ssc,

	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc),

};



static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = {

	.reg_pairs = cdns_pcie_ln_regs_int_ssc,

	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc),

};



/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */

static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {

	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
@@ -1173,13 +1334,52 @@ static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { 


/* refclk100MHz_32b_PCIe_ln_ext_ssc */

static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {

	{0xFC08, SIERRA_DET_STANDEC_A_PREG},

	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},

	{0x1555, SIERRA_DFE_BIASTRIM_PREG},

	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},

	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},

	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},

	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},

	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},

	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},

	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},

	{0x9800, SIERRA_RX_CTLE_CAL_PREG},

	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},

	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}

	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},

	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},

	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},

	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},

	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},

	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},

	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},

	{0x0041, SIERRA_DEQ_GLUT0},

	{0x0082, SIERRA_DEQ_GLUT1},

	{0x00C3, SIERRA_DEQ_GLUT2},

	{0x0145, SIERRA_DEQ_GLUT3},

	{0x0186, SIERRA_DEQ_GLUT4},

	{0x09E7, SIERRA_DEQ_ALUT0},

	{0x09A6, SIERRA_DEQ_ALUT1},

	{0x0965, SIERRA_DEQ_ALUT2},

	{0x08E3, SIERRA_DEQ_ALUT3},

	{0x00FA, SIERRA_DEQ_DFETAP0},

	{0x00FA, SIERRA_DEQ_DFETAP1},

	{0x00FA, SIERRA_DEQ_DFETAP2},

	{0x00FA, SIERRA_DEQ_DFETAP3},

	{0x00FA, SIERRA_DEQ_DFETAP4},

	{0x000F, SIERRA_DEQ_PRECUR_PREG},

	{0x0280, SIERRA_DEQ_POSTCUR_PREG},

	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},

	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},

	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},

	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},

	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}

};



static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
@@ -1316,14 +1516,18 @@ static const struct cdns_sierra_data cdns_map_sierra = { 
	.pcs_cmn_vals = {

		[TYPE_PCIE] = {

			[TYPE_NONE] = {

				[NO_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

			},

		},

	},

	.pma_cmn_vals = {

		[TYPE_PCIE] = {

			[TYPE_NONE] = {

				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,

			},

		},

		[TYPE_USB] = {
@@ -1335,7 +1539,9 @@ static const struct cdns_sierra_data cdns_map_sierra = { 
	.pma_ln_vals = {

		[TYPE_PCIE] = {

			[TYPE_NONE] = {

				[NO_SSC] = &pcie_100_no_ssc_ln_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,

			},

		},

		[TYPE_USB] = {
@@ -1353,14 +1559,18 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { 
	.pcs_cmn_vals = {

		[TYPE_PCIE] = {

			[TYPE_NONE] = {

				[NO_SSC] = &pcie_phy_pcs_cmn_vals,

				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,

			},

		},

	},

	.pma_cmn_vals = {

		[TYPE_PCIE] = {

			[TYPE_NONE] = {

				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,

			},

		},

		[TYPE_USB] = {
@@ -1372,7 +1582,9 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = { 
	.pma_ln_vals = {

		[TYPE_PCIE] = {

			[TYPE_NONE] = {

				[NO_SSC] = &pcie_100_no_ssc_ln_vals,

				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,

				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,

			},

		},

		[TYPE_USB] = {