drm/nouveau/secboot: move code to boot LS falcons to subdevs

#ifndef __NVFW_PMU_H__

#define __NVFW_PMU_H__

struct nv_pmu_args {

	u32 reserved;

	u32 freq_hz;

	u32 trace_size;

	u32 trace_dma_base;

	u16 trace_dma_base1;

	u8 trace_dma_offset;

	u32 trace_dma_idx;

	bool secure_mode;

	bool raise_priv_sec;

	struct {

		u32 dma_base;

		u16 dma_base1;

		u8 dma_offset;

		u16 fb_size;

		u8 dma_idx;

	} gc6_ctx;

	u8 pad;

};

#define NV_PMU_UNIT_INIT                                                   0x07

#define NV_PMU_UNIT_ACR                                                    0x0a

#ifndef __NVFW_SEC2_H__

#define __NVFW_SEC2_H__

struct nv_sec2_args {

	u32 freq_hz;

	u32 falc_trace_size;

	u32 falc_trace_dma_base;

	u32 falc_trace_dma_idx;

	bool secure_mode;

};

#define NV_SEC2_UNIT_INIT                                                  0x01

#define NV_SEC2_UNIT_ACR                                                   0x08

#ifndef __NVKM_CORE_MSGQUEUE_H

#define __NVKM_CORE_MSGQUEUE_H

#include <subdev/secboot.h>

struct nvkm_msgqueue;

/* Hopefully we will never have firmware arguments larger than that... */

#define NVKM_MSGQUEUE_CMDLINE_SIZE 0x100

int nvkm_msgqueue_new(u32, struct nvkm_falcon *, const struct nvkm_secboot *,

		      struct nvkm_msgqueue **);

void nvkm_msgqueue_del(struct nvkm_msgqueue **);

/* useful if we run a NVIDIA-signed firmware */

void nvkm_msgqueue_write_cmdline(struct nvkm_msgqueue *, void *);

#endif

	struct nvkm_falcon_qmgr *qmgr;

	struct nvkm_falcon_cmdq *cmdq;

	struct nvkm_falcon_msgq *msgq;

	struct nvkm_msgqueue *queue;

	struct work_struct work;

	bool initmsg_received;

};

struct nvkm_acr_lsf_func {

	int (*boot)(struct nvkm_falcon *);

	int (*bootstrap_falcon)(struct nvkm_falcon *, enum nvkm_acr_lsf_id);

	int (*bootstrap_multiple_falcons)(struct nvkm_falcon *, u32 mask);

};