Commit 7a13a2ee authored by Yinjun Zhang's avatar Yinjun Zhang Committed by Jakub Kicinski
Browse files

nfp: fix incorrect use of mbox in IPsec code 



The mailbox configuration mechanism requires writing several registers,
which shouldn't be interrupted, so need lock to avoid race condition.

The base offset of mailbox configuration registers is not fixed, it
depends on TLV caps read from application firmware.

Fixes: 859a497f ("nfp: implement xfrm callbacks and expose ipsec offload feature to upper layer")
Signed-off-by: default avatarYinjun Zhang <yinjun.zhang@corigine.com>
Signed-off-by: default avatarSimon Horman <simon.horman@corigine.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent d61615c3

drivers/net/ethernet/netronome/nfp/crypto/ipsec.c

+12 −3
Original line number Diff line number Diff line
@@ -132,23 +132,32 @@ struct nfp_ipsec_cfg_mssg { 
static int nfp_ipsec_cfg_cmd_issue(struct nfp_net *nn, int type, int saidx,

				   struct nfp_ipsec_cfg_mssg *msg)

{

	unsigned int offset = nn->tlv_caps.mbox_off + NFP_NET_CFG_MBOX_SIMPLE_VAL;

	int i, msg_size, ret;



	ret = nfp_net_mbox_lock(nn, sizeof(*msg));

	if (ret)

		return ret;



	msg->cmd = type;

	msg->sa_idx = saidx;

	msg->rsp = 0;

	msg_size = ARRAY_SIZE(msg->raw);



	for (i = 0; i < msg_size; i++)

		nn_writel(nn, NFP_NET_CFG_MBOX_VAL + 4 * i, msg->raw[i]);

		nn_writel(nn, offset + 4 * i, msg->raw[i]);



	ret = nfp_net_mbox_reconfig(nn, NFP_NET_CFG_MBOX_CMD_IPSEC);

	if (ret < 0)

	if (ret < 0) {

		nn_ctrl_bar_unlock(nn);

		return ret;

	}



	/* For now we always read the whole message response back */

	for (i = 0; i < msg_size; i++)

		msg->raw[i] = nn_readl(nn, NFP_NET_CFG_MBOX_VAL + 4 * i);

		msg->raw[i] = nn_readl(nn, offset + 4 * i);



	nn_ctrl_bar_unlock(nn);



	switch (msg->rsp) {

	case NFP_IPSEC_CFG_MSSG_OK:

drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h

+0 −1
Original line number Diff line number Diff line
@@ -403,7 +403,6 @@ 
 */

#define NFP_NET_CFG_MBOX_BASE		0x1800

#define NFP_NET_CFG_MBOX_VAL_MAX_SZ	0x1F8

#define NFP_NET_CFG_MBOX_VAL		0x1808

#define NFP_NET_CFG_MBOX_SIMPLE_CMD	0x0

#define NFP_NET_CFG_MBOX_SIMPLE_RET	0x4

#define NFP_NET_CFG_MBOX_SIMPLE_VAL	0x8