Commit 7a0e7d52 authored by Ahmad Fatoum's avatar Ahmad Fatoum Committed by Jarkko Sakkinen
Browse files

crypto: caam - determine whether CAAM supports blob encap/decap 



Depending on SoC variant, a CAAM may be available, but with some futures
fused out. The LS1028A (non-E) SoC is one such SoC and while it
indicates BLOB support, BLOB operations will ultimately fail, because
there is no AES support. Add a new blob_present member to reflect
whether both BLOB support and the AES support it depends on is
available.

These will be used in a follow-up commit to allow blob driver
initialization to error out on SoCs without the necessary hardware
support instead of failing at runtime with a cryptic

  caam_jr 8020000.jr: 20000b0f: CCB: desc idx 11: : Invalid CHA selected.

Co-developed-by: default avatarMichael Walle <michael@walle.cc>
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Tested-by: Michael Walle <michael@walle.cc> # on ls1028a (non-E and E)
Signed-off-by: default avatarAhmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: default avatarPankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: default avatarJarkko Sakkinen <jarkko@kernel.org>
parent fcd7c269

drivers/crypto/caam/ctrl.c

+15 −2
Original line number Diff line number Diff line
@@ -820,12 +820,25 @@ static int caam_probe(struct platform_device *pdev) 
		return -ENOMEM;

	}



	if (ctrlpriv->era < 10)

	comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ls);

	ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB);



	/*

	 * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support,

	 * but fail when actually using it due to missing AES support, so

	 * check both here.

	 */

	if (ctrlpriv->era < 10) {

		rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &

			   CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;

	else

		ctrlpriv->blob_present = ctrlpriv->blob_present &&

			(rd_reg32(&ctrl->perfmon.cha_num_ls) & CHA_ID_LS_AES_MASK);

	} else {

		rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>

			   CHA_VER_VID_SHIFT;

		ctrlpriv->blob_present = ctrlpriv->blob_present &&

			(rd_reg32(&ctrl->vreg.aesa) & CHA_VER_MISC_AES_NUM_MASK);

	}



	/*

	 * If SEC has RNG version >= 4 and RNG state handle has not been

drivers/crypto/caam/intern.h

+1 −0
Original line number Diff line number Diff line
@@ -92,6 +92,7 @@ struct caam_drv_private { 
	 */

	u8 total_jobrs;		/* Total Job Rings in device */

	u8 qi_present;		/* Nonzero if QI present in device */

	u8 blob_present;	/* Nonzero if BLOB support present in device */

	u8 mc_en;		/* Nonzero if MC f/w is active */

	int secvio_irq;		/* Security violation interrupt number */

	int virt_en;		/* Virtualization enabled in CAAM */

drivers/crypto/caam/regs.h

+3 −1
Original line number Diff line number Diff line
@@ -320,6 +320,7 @@ struct version_regs { 
#define CHA_VER_VID_MASK	(0xffull << CHA_VER_VID_SHIFT)



/* CHA Miscellaneous Information - AESA_MISC specific */

#define CHA_VER_MISC_AES_NUM_MASK	GENMASK(7, 0)

#define CHA_VER_MISC_AES_GCM		BIT(1 + CHA_VER_MISC_SHIFT)



/* CHA Miscellaneous Information - PKHA_MISC specific */
@@ -414,6 +415,7 @@ struct caam_perfmon { 
#define CTPR_MS_PG_SZ_MASK	0x10

#define CTPR_MS_PG_SZ_SHIFT	4

	u32 comp_parms_ms;	/* CTPR - Compile Parameters Register	*/

#define CTPR_LS_BLOB           BIT(1)

	u32 comp_parms_ls;	/* CTPR - Compile Parameters Register	*/

	u64 rsvd1[2];