Commit 79f2056b authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'phy-dp83867-enable-robust-auto-mdix'



Grygorii Strashko says:

====================
net: phy: dp83867: enable robust auto-mdix

Patch 1 - improves link detection when dp83867 PHY is configured in manual mode
by enabling CFG3[9] Robust Auto-MDIX option.

Patch 2 - is minor optimization.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 546b85bb ef87f7da
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+11 −10
Original line number Diff line number Diff line
@@ -95,6 +95,10 @@
#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK	(0x1f << 8)
#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT	8

/* CFG3 bits */
#define DP83867_CFG3_INT_OE			BIT(7)
#define DP83867_CFG3_ROBUST_AUTO_MDIX		BIT(9)

/* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)

@@ -295,7 +299,7 @@ static int dp83867_probe(struct phy_device *phydev)

	phydev->priv = dp83867;

	return 0;
	return dp83867_of_init(phydev);
}

static int dp83867_config_init(struct phy_device *phydev)
@@ -304,10 +308,6 @@ static int dp83867_config_init(struct phy_device *phydev)
	int ret, val, bs;
	u16 delay;

	ret = dp83867_of_init(phydev);
	if (ret)
		return ret;

	/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
	if (dp83867->rxctrl_strap_quirk)
		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
@@ -410,12 +410,13 @@ static int dp83867_config_init(struct phy_device *phydev)
		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
	}

	/* Enable Interrupt output INT_OE in CFG3 register */
	if (phy_interrupt_is_valid(phydev)) {
	val = phy_read(phydev, DP83867_CFG3);
		val |= BIT(7);
	/* Enable Interrupt output INT_OE in CFG3 register */
	if (phy_interrupt_is_valid(phydev))
		val |= DP83867_CFG3_INT_OE;

	val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
	phy_write(phydev, DP83867_CFG3, val);
	}

	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
		dp83867_config_port_mirroring(phydev);