Commit 79d82cbc authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
Browse files

arm64/kexec: Test page size support with new TGRAN range values 



The commit 26f55386 ("arm64/mm: Fix __enable_mmu() for new TGRAN range
values") had already switched into testing ID_AA64MMFR0_TGRAN range values.
This just changes system_supports_[4|16|64]kb_granule() helpers to perform
similar range tests as well. While here, it standardizes page size specific
supported min and max TGRAN values.

Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/1626237975-1909-1-git-send-email-anshuman.khandual@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent ff117646

arch/arm64/include/asm/cpufeature.h

+6 −3
Original line number Diff line number Diff line
@@ -657,7 +657,8 @@ static inline bool system_supports_4kb_granule(void) 
	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN4_SHIFT);



	return val == ID_AA64MMFR0_TGRAN4_SUPPORTED;

	return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX);

}



static inline bool system_supports_64kb_granule(void)
@@ -669,7 +670,8 @@ static inline bool system_supports_64kb_granule(void) 
	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN64_SHIFT);



	return val == ID_AA64MMFR0_TGRAN64_SUPPORTED;

	return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX);

}



static inline bool system_supports_16kb_granule(void)
@@ -681,7 +683,8 @@ static inline bool system_supports_16kb_granule(void) 
	val = cpuid_feature_extract_unsigned_field(mmfr0,

						ID_AA64MMFR0_TGRAN16_SHIFT);



	return val == ID_AA64MMFR0_TGRAN16_SUPPORTED;

	return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) &&

	       (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX);

}



static inline bool system_supports_mixed_endian_el0(void)

arch/arm64/include/asm/sysreg.h

+16 −12
Original line number Diff line number Diff line
@@ -848,11 +848,15 @@ 
#define ID_AA64MMFR0_PARANGE_SHIFT	0



#define ID_AA64MMFR0_TGRAN4_NI			0xf

#define ID_AA64MMFR0_TGRAN4_SUPPORTED	0x0

#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN64_NI			0xf

#define ID_AA64MMFR0_TGRAN64_SUPPORTED	0x0

#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN	0x0

#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN16_NI			0x0

#define ID_AA64MMFR0_TGRAN16_SUPPORTED	0x1

#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN	0x1

#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX	0xf



#define ID_AA64MMFR0_PARANGE_48		0x5

#define ID_AA64MMFR0_PARANGE_52		0x6
@@ -1028,16 +1032,16 @@ 


#if defined(CONFIG_ARM64_4K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN4_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX

#elif defined(CONFIG_ARM64_16K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN16_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	0xF

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX

#elif defined(CONFIG_ARM64_64K_PAGES)

#define ID_AA64MMFR0_TGRAN_SHIFT		ID_AA64MMFR0_TGRAN64_SHIFT

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	0x7

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN

#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX

#endif



#define MVFR2_FPMISC_SHIFT		4