Unverified Commit 79bc3f85 authored by Nam Cao's avatar Nam Cao Committed by Palmer Dabbelt
Browse files

riscv: correct riscv_insn_is_c_jr() and riscv_insn_is_c_jalr() 



The instructions c.jr and c.jalr must have rs1 != 0, but
riscv_insn_is_c_jr() and riscv_insn_is_c_jalr() do not check for this. So,
riscv_insn_is_c_jr() can match a reserved encoding, while
riscv_insn_is_c_jalr() can match the c.ebreak instruction.

Rewrite them with check for rs1 != 0.

Signed-off-by: default avatarNam Cao <namcaov@gmail.com>
Reviewed-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Fixes: ec5f9087 ("RISC-V: Move riscv_insn_is_* macros into a common header")
Link: https://lore.kernel.org/r/20230731183925.152145-1-namcaov@gmail.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 52449c17

arch/riscv/include/asm/insn.h

+13 −2
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ 
#define RVC_INSN_FUNCT4_OPOFF	12

#define RVC_INSN_FUNCT3_MASK	GENMASK(15, 13)

#define RVC_INSN_FUNCT3_OPOFF	13

#define RVC_INSN_J_RS1_MASK	GENMASK(11, 7)

#define RVC_INSN_J_RS2_MASK	GENMASK(6, 2)

#define RVC_INSN_OPCODE_MASK	GENMASK(1, 0)

#define RVC_ENCODE_FUNCT3(f_)	(RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
@@ -245,8 +246,6 @@ __RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL) 
__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)

__RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)

__RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)

__RISCV_INSN_FUNCS(c_jr, RVC_MASK_C_JR, RVC_MATCH_C_JR)

__RISCV_INSN_FUNCS(c_jalr, RVC_MASK_C_JALR, RVC_MATCH_C_JALR)

__RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)

__RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)

__RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
@@ -273,6 +272,18 @@ static __always_inline bool riscv_insn_is_branch(u32 code) 
	return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;

}



static __always_inline bool riscv_insn_is_c_jr(u32 code)

{

	return (code & RVC_MASK_C_JR) == RVC_MATCH_C_JR &&

	       (code & RVC_INSN_J_RS1_MASK) != 0;

}



static __always_inline bool riscv_insn_is_c_jalr(u32 code)

{

	return (code & RVC_MASK_C_JALR) == RVC_MATCH_C_JALR &&

	       (code & RVC_INSN_J_RS1_MASK) != 0;

}



#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))

#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))

#define RV_X(X, s, mask)  (((X) >> (s)) & (mask))