Loading arch/arm/kvm/reset.c +0 −4 Original line number Diff line number Diff line Loading @@ -33,8 +33,6 @@ * Cortex-A15 and Cortex-A7 Reset Values */ static const int cortexa_max_cpu_idx = 3; static struct kvm_regs cortexa_regs_reset = { .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT, }; Loading Loading @@ -64,8 +62,6 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) switch (vcpu->arch.target) { case KVM_ARM_TARGET_CORTEX_A7: case KVM_ARM_TARGET_CORTEX_A15: if (vcpu->vcpu_id > cortexa_max_cpu_idx) return -EINVAL; cpu_reset = &cortexa_regs_reset; vcpu->arch.midr = read_cpuid_id(); cpu_vtimer_irq = &cortexa_vtimer_irq; Loading Loading
arch/arm/kvm/reset.c +0 −4 Original line number Diff line number Diff line Loading @@ -33,8 +33,6 @@ * Cortex-A15 and Cortex-A7 Reset Values */ static const int cortexa_max_cpu_idx = 3; static struct kvm_regs cortexa_regs_reset = { .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT, }; Loading Loading @@ -64,8 +62,6 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) switch (vcpu->arch.target) { case KVM_ARM_TARGET_CORTEX_A7: case KVM_ARM_TARGET_CORTEX_A15: if (vcpu->vcpu_id > cortexa_max_cpu_idx) return -EINVAL; cpu_reset = &cortexa_regs_reset; vcpu->arch.midr = read_cpuid_id(); cpu_vtimer_irq = &cortexa_vtimer_irq; Loading