Commit 7996c5f5 authored by Michael Walle's avatar Michael Walle Committed by Linus Walleij
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pinctrl: microchip-sgpio: lock RMW access



Protect any RMW access to the registers by a spinlock.

Fixes: 7e5ea974 ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO")
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-2-michael@walle.cc


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent d1f2c82f
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+15 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/spinlock.h>

#include "core.h"
#include "pinconf.h"
@@ -116,6 +117,7 @@ struct sgpio_priv {
	u32 clock;
	struct regmap *regs;
	const struct sgpio_properties *properties;
	spinlock_t lock;
};

struct sgpio_port_addr {
@@ -228,6 +230,7 @@ static void sgpio_output_set(struct sgpio_priv *priv,
			     int value)
{
	unsigned int bit = SGPIO_SRC_BITS * addr->bit;
	unsigned long flags;
	u32 clr, set;

	switch (priv->properties->arch) {
@@ -246,7 +249,10 @@ static void sgpio_output_set(struct sgpio_priv *priv,
	default:
		return;
	}

	spin_lock_irqsave(&priv->lock, flags);
	sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static int sgpio_output_get(struct sgpio_priv *priv,
@@ -574,10 +580,13 @@ static void microchip_sgpio_irq_settype(struct irq_data *data,
	struct sgpio_bank *bank = gpiochip_get_data(chip);
	unsigned int gpio = irqd_to_hwirq(data);
	struct sgpio_port_addr addr;
	unsigned long flags;
	u32 ena;

	sgpio_pin_to_addr(bank->priv, gpio, &addr);

	spin_lock_irqsave(&bank->priv->lock, flags);

	/* Disable interrupt while changing type */
	ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
	sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
@@ -594,6 +603,8 @@ static void microchip_sgpio_irq_settype(struct irq_data *data,

	/* Possibly re-enable interrupts */
	sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);

	spin_unlock_irqrestore(&bank->priv->lock, flags);
}

static void microchip_sgpio_irq_setreg(struct irq_data *data,
@@ -604,13 +615,16 @@ static void microchip_sgpio_irq_setreg(struct irq_data *data,
	struct sgpio_bank *bank = gpiochip_get_data(chip);
	unsigned int gpio = irqd_to_hwirq(data);
	struct sgpio_port_addr addr;
	unsigned long flags;

	sgpio_pin_to_addr(bank->priv, gpio, &addr);

	spin_lock_irqsave(&bank->priv->lock, flags);
	if (clear)
		sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
	else
		sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
	spin_unlock_irqrestore(&bank->priv->lock, flags);
}

static void microchip_sgpio_irq_mask(struct irq_data *data)
@@ -832,6 +846,7 @@ static int microchip_sgpio_probe(struct platform_device *pdev)
		return -ENOMEM;

	priv->dev = dev;
	spin_lock_init(&priv->lock);

	reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
	if (IS_ERR(reset))