Commit 79923b43 authored by LeoLiu-oc's avatar LeoLiu-oc Committed by Zheng Zengkai
Browse files

Add MCA supprot for X86_VENDOR_CENTAUR CPUs 

zhaoxin inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I40QDN


CVE: NA

----------------------------------------------------------------

Add MCA support for some Zhaoxin CPUs which use X86_VENDOR_CENTAUR
as vendor ID.

Signed-off-by: default avatarLeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
Reviewed-by: default avatarHanjun Guo <guohanjun@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent e7adcf6c

arch/x86/kernel/cpu/mce/core.c

+14 −25
Original line number Diff line number Diff line
@@ -538,6 +538,7 @@ int mce_usable_address(struct mce *m) 


	/* Checks after this one are Intel/Zhaoxin-specific: */

	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&

	    boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR &&

		boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)

		return 1;
@@ -562,6 +563,7 @@ bool mce_is_memory_error(struct mce *m) 
		return amd_mce_is_memory_error(m);



	case X86_VENDOR_INTEL:

	case X86_VENDOR_CENTAUR:

	case X86_VENDOR_ZHAOXIN:

		/*

		 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
@@ -1155,7 +1157,8 @@ static noinstr bool mce_check_crashing_cpu(void) 


		mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);



		if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {

		if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||

			boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {

			if (mcgstatus & MCG_STATUS_LMCES)

				return false;

		}
@@ -1358,6 +1361,7 @@ noinstr void do_machine_check(struct pt_regs *regs) 
	 * on Intel, Zhaoxin only.

	 */

	if (m.cpuvendor == X86_VENDOR_INTEL ||

		m.cpuvendor == X86_VENDOR_CENTAUR ||

		m.cpuvendor == X86_VENDOR_ZHAOXIN)

		lmce = m.mcgstatus & MCG_STATUS_LMCES;
@@ -1786,7 +1790,8 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 
			quirk_no_way_out = quirk_sandybridge_ifu;

	}



	if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {

	if (c->x86_vendor == X86_VENDOR_CENTAUR ||

		c->x86_vendor == X86_VENDOR_ZHAOXIN) {

		/*

		 * All newer Zhaoxin CPUs support MCE broadcasting. Enable

		 * synchronization with a one second timeout.
@@ -1846,21 +1851,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 
	}

}



static void mce_centaur_feature_init(struct cpuinfo_x86 *c)

{

	struct mca_config *cfg = &mca_cfg;



	 /*

	  * All newer Centaur CPUs support MCE broadcasting. Enable

	  * synchronization with a one second timeout.

	  */

	if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||

	     c->x86 > 6) {

		if (cfg->monarch_timeout < 0)

			cfg->monarch_timeout = USEC_PER_SEC;

	}

}



static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)

{

	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
@@ -1908,9 +1898,6 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 
		break;



	case X86_VENDOR_CENTAUR:

		mce_centaur_feature_init(c);

		break;



	case X86_VENDOR_ZHAOXIN:

		mce_zhaoxin_feature_init(c);

		break;
@@ -1927,6 +1914,7 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 
		mce_intel_feature_clear(c);

		break;



	case X86_VENDOR_CENTAUR:

	case X86_VENDOR_ZHAOXIN:

		mce_zhaoxin_feature_clear(c);

		break;
@@ -2235,6 +2223,7 @@ static void vendor_disable_error_reporting(void) 
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||

		boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||

		boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||

		boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||

		boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)

		return;

arch/x86/kernel/cpu/mce/intel.c

+2 −1
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ static int cmci_supported(int *banks) 
	 * makes sure none of the backdoors are entered otherwise.

	 */

	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&

		boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR &&

		boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)

		return 0;