Commit 798661c7 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlxsw-unified-bridge-conversion-part-6' 

Ido Schimmel says:

====================
mlxsw: Unified bridge conversion - part 6/6

This is the sixth and final part of the conversion of mlxsw to the
unified bridge model. It transitions the last bits of functionality that
were under firmware's responsibility in the legacy model to the driver.
The last patches flip the driver to the unified bridge model and clean
up code that was used to make the conversion easier to review.

Patchset overview:

Patch #1 sets the egress VID for known unicast packets. For multicast
packets, the egress VID is configured using the MPE table. See commit
8c2da081 ("mlxsw: spectrum_fid: Configure egress VID classification
for multicast").

Patch #2 configures the VNI to FID classification that is used during
decapsulation.

Patch #3 configures ingress router interface (RIF) in FID classification
records, so that when a packet reaches the router block, its ingress RIF
is known. Care is taken to configure this in all the different flows
(e.g., RIF set on a FID, {Port, VID} joins a FID that already has a RIF
etc.).

Patch #4 configures the egress VID for routed packets. For such packets,
the egress VID is not set by the MPE table or by an FDB record at the
egress bridge, but instead by a dedicated table that maps {Egress RIF,
Egress port} to a VID.

Patch #5 removes VID configuration from RIF creation as in the unified
bridge model firmware no longer needs it.

Patch #6 sets the egress FID to use in RIF configuration so that the
device knows using which FID to bridge the packet after routing.

Patches #7-#9 add a new 802.1Q family and associated VLAN RIFs. In the
unified bridge model, we no longer need to emulate 802.1Q FIDs using
802.1D FIDs as VNI can be associated with both.

Patches #10-#11 finally flip the driver to the unified bridge model.

Patches #12-#13 clean up code that was used to make the conversion
easier to review.

v2:
* Fix build failure [1] in patch #1.

[1] https://lore.kernel.org/netdev/20220630201709.6e66a1bb@kernel.org/


====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d0bf1fe6 88840d69

drivers/net/ethernet/mellanox/mlxsw/cmd.h

+13 −0
Original line number Diff line number Diff line
@@ -633,6 +633,12 @@ MLXSW_ITEM32(cmd_mbox, config_profile, 
 */

MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1);



/* cmd_mbox_config_set_ubridge

 * Capability bit. Setting a bit to 1 configures the profile

 * according to the mailbox contents.

 */

MLXSW_ITEM32(cmd_mbox, config_profile, set_ubridge, 0x0C, 22, 1);



/* cmd_mbox_config_set_kvd_linear_size

 * Capability bit. Setting a bit to 1 configures the profile

 * according to the mailbox contents.
@@ -792,6 +798,13 @@ MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 
 */

MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1);



/* cmd_mbox_config_profile_ubridge

 * Unified Bridge

 * 0 - non unified bridge

 * 1 - unified bridge

 */

MLXSW_ITEM32(cmd_mbox, config_profile, ubridge, 0x50, 4, 1);



/* cmd_mbox_config_kvd_linear_size

 * KVD Linear Size

 * Valid for Spectrum only

drivers/net/ethernet/mellanox/mlxsw/core.h

+2 −0
Original line number Diff line number Diff line
@@ -295,6 +295,7 @@ struct mlxsw_config_profile { 
		used_max_pkey:1,

		used_ar_sec:1,

		used_adaptive_routing_group_cap:1,

		used_ubridge:1,

		used_kvd_sizes:1;

	u8	max_vepa_channels;

	u16	max_mid;
@@ -314,6 +315,7 @@ struct mlxsw_config_profile { 
	u8	ar_sec;

	u16	adaptive_routing_group_cap;

	u8	arn;

	u8	ubridge;

	u32	kvd_linear_size;

	u8	kvd_hash_single_parts;

	u8	kvd_hash_double_parts;

drivers/net/ethernet/mellanox/mlxsw/pci.c

+5 −0
Original line number Diff line number Diff line
@@ -1235,6 +1235,11 @@ static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 
		mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(

			mbox, profile->adaptive_routing_group_cap);

	}

	if (profile->used_ubridge) {

		mlxsw_cmd_mbox_config_profile_set_ubridge_set(mbox, 1);

		mlxsw_cmd_mbox_config_profile_ubridge_set(mbox,

							  profile->ubridge);

	}

	if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) {

		err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res);

		if (err)

drivers/net/ethernet/mellanox/mlxsw/reg.h

+20 −10
Original line number Diff line number Diff line
@@ -380,7 +380,7 @@ static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 


static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,

					 enum mlxsw_reg_sfd_rec_policy policy,

					 const char *mac, u16 fid_vid,

					 const char *mac, u16 fid_vid, u16 vid,

					 enum mlxsw_reg_sfd_rec_action action,

					 u16 local_port)

{
@@ -389,6 +389,8 @@ static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 
	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);

	mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);

	mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);

	mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false);

	mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid);

	mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);

}
@@ -454,6 +456,7 @@ mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 
	mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);

	mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);

	mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);

	mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true);

	mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);

	mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);

}
@@ -1655,40 +1658,43 @@ MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 


static inline void __mlxsw_reg_svfa_pack(char *payload,

					 enum mlxsw_reg_svfa_mt mt, bool valid,

					 u16 fid)

					 u16 fid, bool irif_v, u16 irif)

{

	MLXSW_REG_ZERO(svfa, payload);

	mlxsw_reg_svfa_swid_set(payload, 0);

	mlxsw_reg_svfa_mapping_table_set(payload, mt);

	mlxsw_reg_svfa_v_set(payload, valid);

	mlxsw_reg_svfa_fid_set(payload, fid);

	mlxsw_reg_svfa_irif_v_set(payload, irif_v);

	mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0);

}



static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port,

						bool valid, u16 fid, u16 vid)

						bool valid, u16 fid, u16 vid,

						bool irif_v, u16 irif)

{

	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;



	__mlxsw_reg_svfa_pack(payload, mt, valid, fid);

	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);

	mlxsw_reg_svfa_local_port_set(payload, local_port);

	mlxsw_reg_svfa_vid_set(payload, vid);

}



static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid,

					   u16 vid)

					   u16 vid, bool irif_v, u16 irif)

{

	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID;



	__mlxsw_reg_svfa_pack(payload, mt, valid, fid);

	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);

	mlxsw_reg_svfa_vid_set(payload, vid);

}



static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid,

					   u32 vni)

					   u32 vni, bool irif_v, u16 irif)

{

	enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID;



	__mlxsw_reg_svfa_pack(payload, mt, valid, fid);

	__mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);

	mlxsw_reg_svfa_vni_set(payload, vni);

}
@@ -1963,7 +1969,8 @@ MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 
static inline void mlxsw_reg_sfmr_pack(char *payload,

				       enum mlxsw_reg_sfmr_op op, u16 fid,

				       u16 fid_offset, bool flood_rsp,

				       enum mlxsw_reg_bridge_type bridge_type)

				       enum mlxsw_reg_bridge_type bridge_type,

				       bool smpe_valid, u16 smpe)

{

	MLXSW_REG_ZERO(sfmr, payload);

	mlxsw_reg_sfmr_op_set(payload, op);
@@ -1973,6 +1980,8 @@ static inline void mlxsw_reg_sfmr_pack(char *payload, 
	mlxsw_reg_sfmr_vv_set(payload, false);

	mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp);

	mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type);

	mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid);

	mlxsw_reg_sfmr_smpe_set(payload, smpe);

}



/* SPVMLR - Switch Port VLAN MAC Learning Register
@@ -7107,10 +7116,11 @@ static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 
}



static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,

					     u16 system_port, u16 vid)

					     u16 system_port, u16 efid, u16 vid)

{

	mlxsw_reg_ritr_sp_if_lag_set(payload, lag);

	mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);

	mlxsw_reg_ritr_sp_if_efid_set(payload, efid);

	mlxsw_reg_ritr_sp_if_vid_set(payload, vid);

}

drivers/net/ethernet/mellanox/mlxsw/spectrum.c

+8 −21
Original line number Diff line number Diff line
@@ -3161,7 +3161,6 @@ static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 
		goto err_ports_create;

	}



	mlxsw_sp->ubridge = false;

	return 0;



err_ports_create:
@@ -3383,24 +3382,15 @@ static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 
	mlxsw_sp_parsing_fini(mlxsw_sp);

}



/* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated

 * 802.1Q FIDs

 */

#define MLXSW_SP_FID_FLOOD_TABLE_SIZE	(MLXSW_SP_FID_8021D_MAX + \

					 VLAN_VID_MASK - 1)



static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {

	.used_max_mid			= 1,

	.max_mid			= MLXSW_SP_MID_MAX,

	.used_flood_tables		= 1,

	.used_flood_mode                = 1,

	.flood_mode			= MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_MIXED,

	.max_fid_flood_tables		= 3,

	.fid_flood_table_size		= MLXSW_SP_FID_FLOOD_TABLE_SIZE,

	.flood_mode                     = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,

	.used_max_ib_mc			= 1,

	.max_ib_mc			= 0,

	.used_max_pkey			= 1,

	.max_pkey			= 0,

	.used_ubridge			= 1,

	.ubridge			= 1,

	.used_kvd_sizes			= 1,

	.kvd_hash_single_parts		= 59,

	.kvd_hash_double_parts		= 41,
@@ -3414,17 +3404,14 @@ static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 
};



static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {

	.used_max_mid			= 1,

	.max_mid			= MLXSW_SP_MID_MAX,

	.used_flood_tables		= 1,

	.used_flood_mode                = 1,

	.flood_mode			= MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_MIXED,

	.max_fid_flood_tables		= 3,

	.fid_flood_table_size		= MLXSW_SP_FID_FLOOD_TABLE_SIZE,

	.flood_mode                     = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,

	.used_max_ib_mc			= 1,

	.max_ib_mc			= 0,

	.used_max_pkey			= 1,

	.max_pkey			= 0,

	.used_ubridge			= 1,

	.ubridge			= 1,

	.swid_config			= {

		{

			.used_type	= 1,