Commit 7973cff7 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Use intel_de_wait_for_*() in cnl+ cdclk programming 



Replace the hand rolled PLL lock bit waits with intel_de_wait_for_*().

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210430153444.29270-6-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 468f9e8d

drivers/gpu/drm/i915/display/intel_cdclk.c

+4 −6
Original line number Diff line number Diff line
@@ -1493,9 +1493,8 @@ static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 
		     BXT_DE_PLL_PLL_ENABLE, 0);



	/* Timeout 200us */

	if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))

		drm_err(&dev_priv->drm,

			"timeout waiting for CDCLK PLL unlock\n");

	if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))

		drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");



	dev_priv->cdclk.hw.vco = 0;

}
@@ -1512,9 +1511,8 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 
	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);



	/* Timeout 200us */

	if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))

		drm_err(&dev_priv->drm,

			"timeout waiting for CDCLK PLL lock\n");

	if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))

		drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");



	dev_priv->cdclk.hw.vco = vco;

}